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???
10/17/07 17:52
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 		 #145859 - re: what happens
Responding to: ???'s previous message
Jan Waclawek said:
... and what happens, if
Save This Code
case (in)
      8'b00000000: out = 2'dx;
      8'b00000001: out = 2'dx;
      8'b00000010: out = 2'dx;
      8'b00000011: out = 2'dx;
[...]
      8'b00110000: out = 2'dx;
      8'b00110001: out = 2'b01;
      8'b00110010: out = 2'dx;
[...]

      8'b10101011: out = 2'dx;
      8'b10101100: out = 2'b10;
      8'b10101101: out = 2'dx;
[...]
      8'b11110100: out = 2'dx;
      8'b11110101: out = 2'b11;
      8'b11110110: out = 2'dx;
[...]
      8'b11111110: out = 2'dx;
      8'b11111111: out = 2'dx;
      endcase

?

If you specify all 256 cases, then you don't get a latch. And if it was in a synchronous always block, then it doesn't matter, anyway.

However: you NEVER want to assign unknown to a wire or reg in any code you intend to synthesize.

-a

List of 147 messages in thread
TopicAuthorDate
Getting Started With FPGAs, Part II            01/01/70 00:00      
   I didn't find it too big a job ... YMMV, of course            01/01/70 00:00      
   when it doesnt work            01/01/70 00:00      
      I'd guess...            01/01/70 00:00      
         Curses            01/01/70 00:00      
   OP Update 1 of ???            01/01/70 00:00      
      On your way ...            01/01/70 00:00      
         Not windows this time?            01/01/70 00:00      
            Not Windows every time, anyway            01/01/70 00:00      
      re: OP Update            01/01/70 00:00      
         what might be helpful before you get too far along            01/01/70 00:00      
   OP Update 2 of ???            01/01/70 00:00      
      re: update            01/01/70 00:00      
         The Verilog == C trap            01/01/70 00:00      
            re: The Verilog == C trap            01/01/70 00:00      
               Thinking hardware            01/01/70 00:00      
                  I read somewhere ...            01/01/70 00:00      
                  re: Thinking Hardware            01/01/70 00:00      
               One reason why HDL isnt the same as software            01/01/70 00:00      
                  Have I got this right?            01/01/70 00:00      
                     re: Have I got this right?            01/01/70 00:00      
                        re: re: Have I got this right?            01/01/70 00:00      
                           re: OT            01/01/70 00:00      
                        Nothing\'s perfect            01/01/70 00:00      
                        The thing to watch with FPGA's            01/01/70 00:00      
   OP Update 3 of ?            01/01/70 00:00      
      have you looked at the resource utilization?            01/01/70 00:00      
         Just a little bit            01/01/70 00:00      
            On a slightly different note..            01/01/70 00:00      
               the lesson ...            01/01/70 00:00      
               HDL coding to "help" the synthesizer            01/01/70 00:00      
         Please clarify            01/01/70 00:00      
            think hardware            01/01/70 00:00      
               this sounds like...            01/01/70 00:00      
                  re: this sounds like            01/01/70 00:00      
               Please clarify again            01/01/70 00:00      
                  for purpose of understanding ... YES            01/01/70 00:00      
                  answer            01/01/70 00:00      
      double assignment            01/01/70 00:00      
         Good catch, I think            01/01/70 00:00      
            re: Good Catch            01/01/70 00:00      
      block vs nonblocking            01/01/70 00:00      
         I have unplugged my eval board            01/01/70 00:00      
            re: Unplugged            01/01/70 00:00      
   OP Update 4 of ?            01/01/70 00:00      
      Another question about the counter            01/01/70 00:00      
         what's wrong            01/01/70 00:00      
            \'initial\' block            01/01/70 00:00      
               general Verilog coding advice            01/01/70 00:00      
                  Wow            01/01/70 00:00      
            Where does "reset" come from?            01/01/70 00:00      
   OP Dumb Question 1 of ?            01/01/70 00:00      
      look at it in the other way            01/01/70 00:00      
         But isn\'t it out of spec?            01/01/70 00:00      
            If you look more closely at the spec ...            01/01/70 00:00      
         which tools?            01/01/70 00:00      
            fanout exceeded            01/01/70 00:00      
               device dependence            01/01/70 00:00      
      newer data sheet?            01/01/70 00:00      
      Metastability            01/01/70 00:00      
         ... and contact bounce            01/01/70 00:00      
            That might not be a worry ...            01/01/70 00:00      
               Thanks            01/01/70 00:00      
   OP Update 5 of ?            01/01/70 00:00      
      do you mean, adaptive threshold?            01/01/70 00:00      
         Yes            01/01/70 00:00      
            PicoBlaze            01/01/70 00:00      
               Andy ... about that PicoBlaze ...            01/01/70 00:00      
                  re: about picoblaze            01/01/70 00:00      
         the boundary is quite arbitrary            01/01/70 00:00      
            Yes            01/01/70 00:00      
   OP Update 6 of ?            01/01/70 00:00      
      a better way            01/01/70 00:00      
   OP Update 7 of ?            01/01/70 00:00      
      OP Update 7.01            01/01/70 00:00      
         excessive skew warning            01/01/70 00:00      
            Offensive code here            01/01/70 00:00      
               On a slightly different note            01/01/70 00:00      
                  whatizit?            01/01/70 00:00      
                  free vs paid-for ModelSim            01/01/70 00:00      
               reason for the skew warning            01/01/70 00:00      
                  error            01/01/70 00:00      
                  I\\\'m drinking from a fire hose!            01/01/70 00:00      
                     fIREHOSE            01/01/70 00:00      
                        Faucet            01/01/70 00:00      
                           faucet            01/01/70 00:00      
                              Slow drip            01/01/70 00:00      
                                 I have no particular interest in this - but            01/01/70 00:00      
                                    Famous last words...            01/01/70 00:00      
                                       sure, I take your point - but            01/01/70 00:00      
                                 What libraries you use in VHDL            01/01/70 00:00      
                                    std_logic_arith vs numeric_std            01/01/70 00:00      
                              I found the FM!            01/01/70 00:00      
                                 Development System Reference Guide            01/01/70 00:00      
                           Another slow drip            01/01/70 00:00      
                              doubts            01/01/70 00:00      
                              I am not surprised it doesn\'t find that            01/01/70 00:00      
                              I was surprised            01/01/70 00:00      
                              If you want to see how the logic was synthesized            01/01/70 00:00      
                                 Don't cares worked for me            01/01/70 00:00      
                                    Not quite what I meant            01/01/70 00:00      
                                       Bummer            01/01/70 00:00      
                                          I wouldn't worry about minimizing            01/01/70 00:00      
                                             Thanks            01/01/70 00:00      
                              re: drip            01/01/70 00:00      
                                 re: re: drip            01/01/70 00:00      
                                    huh?            01/01/70 00:00      
                                       re: huh?            01/01/70 00:00      
                                          defaults?            01/01/70 00:00      
                                             re: defaults?            01/01/70 00:00      
                                             ***** Interesting result! ******            01/01/70 00:00      
                                          challenge            01/01/70 00:00      
                                             unknown is not don't care            01/01/70 00:00      
                                                A noob question            01/01/70 00:00      
                                                   similar noob question            01/01/70 00:00      
                                                      re: what happens            01/01/70 00:00      
                                                   You should get a latch            01/01/70 00:00      
                                                   re: a noob question            01/01/70 00:00      
                                                      Not really answered            01/01/70 00:00      
                                                         I'd guess...            01/01/70 00:00      
                           Simulator question            01/01/70 00:00      
                              what you are seeing            01/01/70 00:00      
                                 Thanks, Jez            01/01/70 00:00      
                                    check the logic!            01/01/70 00:00      
                                       That's good news            01/01/70 00:00      
                                          this might make the key difference            01/01/70 00:00      
                                             Two flavors of \"big\"            01/01/70 00:00      
                                                drop the comments :-)            01/01/70 00:00      
                                             as has been recommended ...            01/01/70 00:00      
                                          My confidence in XILINX' simulator is low            01/01/70 00:00      
                                             Xilinx vs. ModelSim            01/01/70 00:00      
                                                It's worth using ModelSim just for the features            01/01/70 00:00      
                                          behavioral is good,kind of            01/01/70 00:00      
                                             re: behavioral is good, kind of            01/01/70 00:00      
                                       Double post. Oops.            01/01/70 00:00      
                                 not so simple            01/01/70 00:00      
                              re: Simulator Question: ANSWER            01/01/70 00:00      
                                 re: ANSWER            01/01/70 00:00      
                                 re: ANSWER, Part II            01/01/70 00:00      
                        Long time            01/01/70 00:00      
      one more comment            01/01/70 00:00      
   OP Update 8 of ?            01/01/70 00:00      
      its supposed to make things easier to debug            01/01/70 00:00      
      one way vs the other way            01/01/70 00:00      
         re: Them two ways            01/01/70 00:00      
   OP Update 9 of ?            01/01/70 00:00      
   OP Update 10 of 10            01/01/70 00:00      

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