behavioral simulation is good because it works exactly as the hdl says it should so its used to check the logic of a design, functioal sumulations is slower and more difficult to interpret as the delays shift the edges around, but it is possible to have a behavioral simulation with timing delays added artificaily so its a kind of halfway house,its not as slow as a full functional simualtion and its more accurate than a behavioral one.

VHDL allows signal assignments to include delay specifications, in the form of an after clause. The after clause allows you to model the behavior of gate and wire delays in a circuit. This is very useful if you are developing simulation models or if you want to include estimated delays in your synthesizable design description. The following are two examples of delay specifications associated with signal assignments:

Y1 <= not (A and B) after 7 ns;

Y2 <= not (A and B) transport after 7 ns;

These two assignments demonstrate the two fundamental types of delay specifications available in VHDL: inertial and transport.

Inertial delay is intended to model the delay through a gate, in which there is some minimum pulse length that must be maintained before an event is propogated.

Transport delay, on the other hand, models the delay on a wire, so pulses of any width are propogated.

For design descriptions intended for synthesis, you will probably not bother to use delay specifications such as these. A circuit produced as a result of synthesis is unlikely to have timing characteristics that can be accurately predicted (or specified) up front. In fact, all synthesis tools in use as of this writing ignore the after clause completely. (If you have a general idea of the timing characteristics of your synthesis target—be it an FPGA chip or a high-complexity ASIC—you can use delay specifications to improve the accuracy of your initial simulation. Just be aware that anything you annotate prior to synthesis will be little more than a guess.)

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