Well, that's encouraging, and certainly what one would hope.

However, as I mentioned, the thing that got me going on all this was a case where the output from the Xilinx simulator didn't seem to match the Verilog, while the output from ModelSim running the exact same source code was different, and did match what I expected. That says to me that either:

1. I'm doing something wrong, or
2. One or both of the simulators is goofed up, or
3. I stumbled upon a case where the behavioral simulation isn't sufficient for checking the logic.

Of course the smart money is on #1.

The design that acted differently in the two different simulators was a bit too big to post. I'll see if I can whittle it down to something manageable that still shows the problem so that then
maybe somebody can explain what's going on.

-- Russ