From what I'm aware of, you still need to be careful of metastability. for those who do not know what metastability is:
consider a D type flip flop and the D input changes too close to the clock transition (violates the setup & hold time) -what will the flip/flop do?

1. flip to the right state
2. flip to the opposite state
3. oscillate for a while

In a perfectly synchronous system the violation should not happen as you design the circuit to adhere to the setup and hold times. This is why you have synchronous circuits! But real world designs need to get inputs from outside of this cosy, synchronous world and these inputs may not be able to follow the setup and hold rules. Obviously we don't want the f/f to oscillate or go to the wrong state - statistically we can't guarantee this. The usual solution is to put a synchroniser on the input in question to lessen the possibility of a metastable state.

google turned up this:

http://www.asic-world.com/tidbits/m...blity.html

http://personal.ee.surrey.ac.uk/Personal/...0000000000