| ??? 09/29/07 20:12 Read: times |
#145114 - HDL coding to "help" the synthesizer Responding to: ???'s previous message |
Russell Bull said:
So the net result was that I had to restructure my thinking on designed logic in fpgas - by embracing the fpga way of doing things - if you need a register array, don't use an array of registers - use a ram block. How all this translates into Verilog or VHDL I'm not sure (I originally used schematic capture for fpga design) as I haven't done anything in the VHDL/Verilog. This sounds like a very important point, and it seems like it applies directly to the FIFO part of my Morse code decoder. I'm wondering if one of the HDL experts could chime in and explain (or, just as good, give a reference to something that explains) "how all this translates into Verilog or VHDL". Is this something where you write what you want and trust the synthesizer to do what's best, or are there ways to give it helpful hints? I have the same sort of question about implementing a lookup table (also a part of the Morse code decoder). The naive, no-brainer way seems to be to use a big case statement. I did some throw-away experiments with case statements the other day, and it seemed like sometimes the synthesizer would put the lookup table into what it called (on the RTL schematic) a ROM, and sometimes it would just make a big network of gates. I never did discover what I was doing one way or another in the Verilog source code to make the synthesizer choose one or the other of the two implementations (or even if maybe the only difference was how it was rendering the RTL schematic). -- Russ |
