Ooh! This is interesting--and shows the value to a beginner like me of these seemingly trivial exercises.

Yes, the example does compile. It also works when I go ahead and implement it in the FPGA and look at the output with a 'scope.

I also think the example is correct, because it uses what Verilog calls blocking assignments, which are defined to occur in sequential order like in C, and not in parallel like I think you are thinking. I'm still a little bit fuzzy on this, but I think this page explains it fairly well.

Now what's surprising is that when I change the example to use non-blocking assignments, which do occur in parallel, it still compiles and it still works when I implement it on the hardware! As you have noted, this seems wrong. This seems to me like something very fundamental and very important, so I will definitely play with it further and report back here. In the meantime, maybe one of the experts will chime in and give us a hint?

-- Russ

PS: The synthesizer seems to implement 'clockDivider' as an array of D flip-flops, and I did notice that it does the assignment to zero by asserting the "clear" input on all the flip-flops rather than clocking in a "real" zero through the D inputs. Maybe this has something to do with why it happens to work with the non-blocking assignments.

PPS: I haven't tried either example on the simulator. Maybe it would be more picky somehow and at least give a warning?