Yes, there is a MUCH better way.

There is NEVER a need to "include" a Verilog module in another module's source file.

Create separate files for each module.

In your test bench source, you instantiate the FPGA top-level module. There's no need to "include" a "header" file, as the simulation tool is smart enough to know how to start at the top of the hierarchy and drill down.

Same for your synthesizable code ... you tell the synthesis tool which module is the top level, and it will sort it all out for you.



Two things:

a) Instead of using `defines, use parameters, especially for things that are obviously parameterizable like bus widths. This allows you to use defparams in a higher-level module to override the parameters. You can set the value of the parameter (as it appears on the top-level module) from a command-line in both simulation and synthesis. This also makes it unnecessary to include a "header" file with your defined constants. This also leads to:

b) Consider using the modern Verilog-2001-style (so-called "ANSI-C") module definitions. For example, instead of

module MarkSpaceTimer (clock, rawInput, eventType, eventDuration, newEvent);

    input  clock;				// 20 µs (50 KHz) clock
    input  rawInput;				// Raw Morse code signal
    output eventType;				// MARK (1) or SPACE (0)
    output eventDuration;			// Length of mark or space, in
						//  20 µs units
    output newEvent;				// Pulsed once for each event

simply do

module MarkSpaceTimer 
  #(parameter TIME_WIDTH = 16)
   (input  wire clock,				// 20 µs (50 KHz) clock
    input  wire rawInput,			// Raw Morse code signal
    output reg [TIME_WIDTH-1 : 0] eventType,	// MARK (1) or SPACE (0)
    output reg [TIME_WIDTH-1 : 0] eventDuration,// Length of mark or space, in
						//  20 µs units
    output reg newEvent);			// Pulsed once for each event

-a