There's a maximal clock frequency that you cannot exceed.

Now, I don't have my spec for LS logic on hand at the moment, but I do have the ALS spec, and it specifies the D setup time to be 15 ns with a maximal clock frequency of 34 MHz.

As it happens, in the old TI TTL Data Book Vol. 3, (1984) it also has a clock-to-Q interval of 5-16 ns for rising Q and 7-18 ns for falling Q.

If you consider what's inside a '74, it's clear that somewhere on the order of half the maximal clock period would have to be the limit on clock-to-Q. In an FPGA, there are lookup tables that determine what the response to the inputs will be. Consider that the logic cell is really a RAM with feedback. Now, if the output is registered with a clocked flipflop, the only thing that matters is the setup time and the maximal clock frequency. I think that maximal frequency is specified in the device data sheet. Consequently, if you meet the phase-relationship set forth by the setup time and don't clock the flipflop any faster than it can tolerate, you'll have no worries.

With TTL, it was important to consider what lay in side the IC. With LUT-based programmable logic, it's not so important. I did find some relevant numbers in DS312-3 (v3.2) May 19, 2006, page 126.

RE