| ??? 09/28/07 07:33 Read: times |
#145058 - fanout exceeded Responding to: ???'s previous message |
Jan Waclawek said:
As far as FPGAs are concerned, we were discussing the very same topic with my "personal FPGA guru" yesterday - and he told me, that the cheap tools he is using sometimes s***w up the clock (split it to multiple branches) and this sort of circuits if fed from two different clock branches then sometimes cease to work properly. Andy Peters said: Dunno the name (I can ask) - came with the Actel kit he is using.
What tools? Andy Peters said:
I haven't seen Brand A or Brand X's tools do bad things to clocks like that, unless I've either run out of global clock buffers or I've explicitly told the tools not to route something on a clock line. It might be related. He mentioned something about exceeded fanouts. Andy Peters said:
Bad descriptions can also result in weird branches, but the tools will tell you when it tries to route a clock line on non-global resources. This might quite well have happened too. The whole discussion started from my questions on how device-dependent an implementation of XYZ has to be in VHDL. It seems to me (and him), that unless one follows a certain methodology for a certain brand/family of FPGAs, one can run quickly into problems like these. And, the main trouble is, that he has no time nor money to take courses for that particular chip and tool (which for him was a one-time job anyway, so it simply does not pay out in no means). Eventually, he managed to get it working despite of the fact that it is most probably written in an incorrect way. JW |
