For reference:

    case (in)
      8'b00110001: out = 2'b01;
      8'b10101100: out = 2'b10;
      8'b11110101: out = 2'b11;
      default:     out = 2'dx;
      endcase

Uh, oh! One of us is going to learn something pretty soon here. Probably me, but I don't see your point just yet. Here's how I'm thinking about it:

Bits [0] and [7] are sufficient by themselves to distinguish among the three specified input vectors. Therefore, if we simply connect in[7] to out[1] and in[0] to out[0] with wires like so:

then out will be correct for the three specified input vectors. So far, so good. For all other possible input vectors, the default says that we don't care what the output is, so no further logic is needed to accommodate them.

Maybe my problem is that I have a faulty understanding of what it means in Verilog to say "out = 2'dx;" In any case, I think we can get to the bottom of this if you will undertake this challenge: Please give an input vector where the above circuit doesn't do what the Verilog code says, and explain how the circuit needs to be modified to work correctly for that vector.

Thanks,

-- Russ