| ??? 09/28/07 00:00 Read: times |
#145043 - newer data sheet? Responding to: ???'s previous message |
Russ Cooper said:
Here's a silly question from somebody who ought to know better. Suppose you have the following circuit, which on the surface looks like a no-brainer:
My old Texas Instruments TTL Data Book for Design Engineers specifies a minimum input hold time of 5 ns for the 74LS74A. For the clock-to-Q propagation delay, it gives a "typical" value of 14 ns, but doesn't specify a minimum propagation delay at all. It seems that you need to guarantee that the clock-to-Q propagation delay is at least as long as the minimum required input hold time in order to be sure the circuit will work reliably. Am I missing something, or is this circuit really not kosher? Aye, there's the rub. No, a minimum clock-to-out is never specified. That's why they provide a "typical" delay, even though everyone knows you should never depend on it. But since the typical delay is triple the hold time, it's considered OK to use it for a hold-time calculation. Of course if you put a logic gate in between the two flops, you increase the prop delay and that makes meeting the hold time requirement easier. So ... positive hold times: one more reason why old-skool TTL logic is obsolete! Newer parts have a zero hold-time requirement. Now the real question: In the land of FPGAs, do the software tools help you avoid problems like this, or at least catch them and point them out? If not, how in the world do you deal with them? FPGAs have properly-designed flip-flops which guarantee zero or negative hold time, so all internal stuff will work assuming you always meet prop delay (frequency) constraints. -a |
