??? 09/25/07 02:55 Modified: 09/25/07 02:58 Read: times |
#144946 - \'initial\' block Responding to: ???'s previous message |
Andy said:
You just fell into the trap of thinking that the Verilog initial statement is (or can be used as) a reset. Again, thanks for the help. The plot thickens. As it turns out, I didn't just fall into that trap. I actually thought I read somewhere that the simulator would run the 'initial' block once before it did anything else, and that the synthesizer would ignore the 'initial' block completely. I have no idea if I can find again where I read that, but I'll try. It would be interesting to see what it really said. -- Russ |