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???
09/06/07 05:19
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#144068 - I didn't find it too big a job ... YMMV, of course
Responding to: ???'s previous message
Russ Cooper said:
In a separate thread, which had already wandered off-topic far enough ...

Richard said:
I'm not a big believer in those micro-exercises, e.g. blink a LED, or whatever.

I'm surprised. I would've pegged you as one of the "walk before you try to run" crowd. As near as I can tell, before I see any delightfully blinking LEDs, I'll have to

Learn enough Verilog to describe some hardware that makes them blink.

I'd wonder why you'd want to bother with Verilog at all. If you're a 'C' programmer, you'll be sucked into one trap after another because of syntactic similarities. IMHO, you're better off with VHDL, which, BTW, is much more widely used throughout the world.

Figure out how to use the tools compile it (or whatever you call the process of translating the source code into whatever goes into the FPGA).

A little reading and a fifteen minutes with the software, and you'll be just fine.

Figure out how to get whatever goes into the FPGA into the FPGA. When it doesn't work, figure out why.

The only thing you're likely to do wrong is to plug the cable in backward. The simulator is very good, and will show you what's wrong well in advance of any actual implementation.

Given that I'm starting from the very leading edge of the proverbial Square One, I think it would be crazy in the beginning to try anything but the simplest exercise.

A lot depends on what's on the board you're using. The board can make it very easy or very hard.

-- Russ


I'd spend a little time thinking about the assumption that blinking an LED is much less complicated (Is is somewhat more complicated, but not much.) than displaying a counter on a 7-segment display. It involves a counter, which is a registered device, a HEX=>7-segment encoder, which is a combinatorial device, and one additional tap. That additional tap, of course, could be your blinking LED, so you actually build it along the way.

What you've apparently overlooked is the tools that are at your disposal in, say, the XILINX Webpack, or the Altera Quartus-II Web edition, both of which are free downloadable tools. I don't know about Quartus, but the free XILINX tool allows you to choose either Verilog or VHDL, but not both. If you buy a copy of the "real" deal, I believe you can use both. Both ALTERA and XILINX use ModelSim, so you can simulate and "see" your probable results in minutes. That way you can design and simulate each module as a confidence building measure before you integrate the, in this case, four modules.

You have the ability in either tool suite, to enter your design, simulate it, and program your target device. Once I figured out how to operate the XILINX tools, it took me about half an hour to get to where I could simulate my design of a long counter that reduced the on-board 80 MHz clock to 40 Hz. That's my backplane drive, and it's XOR'd with the 7-segment code to the LCD. Since I wanted HEX display capability, I had to build a new encoder. That took about 15 minutes including the 10 seconds to make a symbol of it so I could put it in a schematic. Figuring out how to program the device was not particularly difficult either. It took me two tries, about a minute each. The most time-consuming part of the exercise was writing the "user configuration file" which, among other things, defines the pin usage. IIRC, the whole job, from opening the box for the EVK to having the running exercise, took little more than an hour. Of course, I'd already figured out how to work the development tools. I did cheat a bit, as I'd been using VHDL to create testbenches for some time.

TO make an LED blink, you still have to generate a counter that divides the fast oscillator down to a rate that you can comfortably observe, and you have to prepare the UCF, though it would be a mite shorter. Since the counter would probably like to count at 1 Hz, that will blink the LED just fine.

If you want to make a LED blink, go ahead. This thing was my first VHDL exercise and I wanted to see whether I could make some use of all the features included on the evaluation board I'd purchased. When I was in college, nobody had thought of HDL's yet, and, in fact, the "transistor radio" was still fairly new, so I had to learn VHDL on my own. Since its popularity is increasing worldwide, while Verilog is used primarily in the U.S, and since VHDL is more "feature-rich," I figured it was a better choice.

For learning the HDL, it's probably easier to start with a CPLD in which you can "leave" your configuration without having to be connected to the PC-bound JTAG cable. That way you can work out, with a 'scope or whatever, anything you may have done wrong. You can build a pretty fancy state machine in a 72 macrocell CPLD, or two or more of them, running simultaneously.

You can do lots with the current FPGA eval kits, but they're often encumbered with devices that eat up pins you might want for something else, and often haven't enough of anything to allow you to do what you want. I'd recommend you read the fine print before buying an eval kit, not because they're expensive ... they're not ... but because of the confusion and disappointment that can result if you get one that's unsuited to your purpose.

For learning an HDL, the easiest thing is to get a low-cost CPLD eval board and work with that for a while. It won't have features on board that get in the way. I'd recommend the DIGILENT <www.digilentinc.com> XC2XL board (~$50). It even has a prototype area that you could use for your LED or whatever. You can buy the FPGA eval kit later, but I'd caution you to consider the expansion capability, i.e, what sort of connectors it has. If you have to use a dedicated connector, rather than a generic one, it can quickly become a pain in the gluteus maximus. Those older DIGILENT boards had 40-pin connectors compatible with discarded IDE cables. I've found them quite useable.

RE




List of 147 messages in thread
TopicAuthorDate
Getting Started With FPGAs, Part II            01/01/70 00:00      
   I didn't find it too big a job ... YMMV, of course            01/01/70 00:00      
   when it doesnt work            01/01/70 00:00      
      I'd guess...            01/01/70 00:00      
         Curses            01/01/70 00:00      
   OP Update 1 of ???            01/01/70 00:00      
      On your way ...            01/01/70 00:00      
         Not windows this time?            01/01/70 00:00      
            Not Windows every time, anyway            01/01/70 00:00      
      re: OP Update            01/01/70 00:00      
         what might be helpful before you get too far along            01/01/70 00:00      
   OP Update 2 of ???            01/01/70 00:00      
      re: update            01/01/70 00:00      
         The Verilog == C trap            01/01/70 00:00      
            re: The Verilog == C trap            01/01/70 00:00      
               Thinking hardware            01/01/70 00:00      
                  I read somewhere ...            01/01/70 00:00      
                  re: Thinking Hardware            01/01/70 00:00      
               One reason why HDL isnt the same as software            01/01/70 00:00      
                  Have I got this right?            01/01/70 00:00      
                     re: Have I got this right?            01/01/70 00:00      
                        re: re: Have I got this right?            01/01/70 00:00      
                           re: OT            01/01/70 00:00      
                        Nothing\'s perfect            01/01/70 00:00      
                        The thing to watch with FPGA's            01/01/70 00:00      
   OP Update 3 of ?            01/01/70 00:00      
      have you looked at the resource utilization?            01/01/70 00:00      
         Just a little bit            01/01/70 00:00      
            On a slightly different note..            01/01/70 00:00      
               the lesson ...            01/01/70 00:00      
               HDL coding to "help" the synthesizer            01/01/70 00:00      
         Please clarify            01/01/70 00:00      
            think hardware            01/01/70 00:00      
               this sounds like...            01/01/70 00:00      
                  re: this sounds like            01/01/70 00:00      
               Please clarify again            01/01/70 00:00      
                  for purpose of understanding ... YES            01/01/70 00:00      
                  answer            01/01/70 00:00      
      double assignment            01/01/70 00:00      
         Good catch, I think            01/01/70 00:00      
            re: Good Catch            01/01/70 00:00      
      block vs nonblocking            01/01/70 00:00      
         I have unplugged my eval board            01/01/70 00:00      
            re: Unplugged            01/01/70 00:00      
   OP Update 4 of ?            01/01/70 00:00      
      Another question about the counter            01/01/70 00:00      
         what's wrong            01/01/70 00:00      
            \'initial\' block            01/01/70 00:00      
               general Verilog coding advice            01/01/70 00:00      
                  Wow            01/01/70 00:00      
            Where does "reset" come from?            01/01/70 00:00      
   OP Dumb Question 1 of ?            01/01/70 00:00      
      look at it in the other way            01/01/70 00:00      
         But isn\'t it out of spec?            01/01/70 00:00      
            If you look more closely at the spec ...            01/01/70 00:00      
         which tools?            01/01/70 00:00      
            fanout exceeded            01/01/70 00:00      
               device dependence            01/01/70 00:00      
      newer data sheet?            01/01/70 00:00      
      Metastability            01/01/70 00:00      
         ... and contact bounce            01/01/70 00:00      
            That might not be a worry ...            01/01/70 00:00      
               Thanks            01/01/70 00:00      
   OP Update 5 of ?            01/01/70 00:00      
      do you mean, adaptive threshold?            01/01/70 00:00      
         Yes            01/01/70 00:00      
            PicoBlaze            01/01/70 00:00      
               Andy ... about that PicoBlaze ...            01/01/70 00:00      
                  re: about picoblaze            01/01/70 00:00      
         the boundary is quite arbitrary            01/01/70 00:00      
            Yes            01/01/70 00:00      
   OP Update 6 of ?            01/01/70 00:00      
      a better way            01/01/70 00:00      
   OP Update 7 of ?            01/01/70 00:00      
      OP Update 7.01            01/01/70 00:00      
         excessive skew warning            01/01/70 00:00      
            Offensive code here            01/01/70 00:00      
               On a slightly different note            01/01/70 00:00      
                  whatizit?            01/01/70 00:00      
                  free vs paid-for ModelSim            01/01/70 00:00      
               reason for the skew warning            01/01/70 00:00      
                  error            01/01/70 00:00      
                  I\\\'m drinking from a fire hose!            01/01/70 00:00      
                     fIREHOSE            01/01/70 00:00      
                        Faucet            01/01/70 00:00      
                           faucet            01/01/70 00:00      
                              Slow drip            01/01/70 00:00      
                                 I have no particular interest in this - but            01/01/70 00:00      
                                    Famous last words...            01/01/70 00:00      
                                       sure, I take your point - but            01/01/70 00:00      
                                 What libraries you use in VHDL            01/01/70 00:00      
                                    std_logic_arith vs numeric_std            01/01/70 00:00      
                              I found the FM!            01/01/70 00:00      
                                 Development System Reference Guide            01/01/70 00:00      
                           Another slow drip            01/01/70 00:00      
                              doubts            01/01/70 00:00      
                              I am not surprised it doesn\'t find that            01/01/70 00:00      
                              I was surprised            01/01/70 00:00      
                              If you want to see how the logic was synthesized            01/01/70 00:00      
                                 Don't cares worked for me            01/01/70 00:00      
                                    Not quite what I meant            01/01/70 00:00      
                                       Bummer            01/01/70 00:00      
                                          I wouldn't worry about minimizing            01/01/70 00:00      
                                             Thanks            01/01/70 00:00      
                              re: drip            01/01/70 00:00      
                                 re: re: drip            01/01/70 00:00      
                                    huh?            01/01/70 00:00      
                                       re: huh?            01/01/70 00:00      
                                          defaults?            01/01/70 00:00      
                                             re: defaults?            01/01/70 00:00      
                                             ***** Interesting result! ******            01/01/70 00:00      
                                          challenge            01/01/70 00:00      
                                             unknown is not don't care            01/01/70 00:00      
                                                A noob question            01/01/70 00:00      
                                                   similar noob question            01/01/70 00:00      
                                                      re: what happens            01/01/70 00:00      
                                                   You should get a latch            01/01/70 00:00      
                                                   re: a noob question            01/01/70 00:00      
                                                      Not really answered            01/01/70 00:00      
                                                         I'd guess...            01/01/70 00:00      
                           Simulator question            01/01/70 00:00      
                              what you are seeing            01/01/70 00:00      
                                 Thanks, Jez            01/01/70 00:00      
                                    check the logic!            01/01/70 00:00      
                                       That's good news            01/01/70 00:00      
                                          this might make the key difference            01/01/70 00:00      
                                             Two flavors of \"big\"            01/01/70 00:00      
                                                drop the comments :-)            01/01/70 00:00      
                                             as has been recommended ...            01/01/70 00:00      
                                          My confidence in XILINX' simulator is low            01/01/70 00:00      
                                             Xilinx vs. ModelSim            01/01/70 00:00      
                                                It's worth using ModelSim just for the features            01/01/70 00:00      
                                          behavioral is good,kind of            01/01/70 00:00      
                                             re: behavioral is good, kind of            01/01/70 00:00      
                                       Double post. Oops.            01/01/70 00:00      
                                 not so simple            01/01/70 00:00      
                              re: Simulator Question: ANSWER            01/01/70 00:00      
                                 re: ANSWER            01/01/70 00:00      
                                 re: ANSWER, Part II            01/01/70 00:00      
                        Long time            01/01/70 00:00      
      one more comment            01/01/70 00:00      
   OP Update 8 of ?            01/01/70 00:00      
      its supposed to make things easier to debug            01/01/70 00:00      
      one way vs the other way            01/01/70 00:00      
         re: Them two ways            01/01/70 00:00      
   OP Update 9 of ?            01/01/70 00:00      
   OP Update 10 of 10            01/01/70 00:00      

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