Okay, let me guess. The problem is that the path through the OR tree could be much shorter for that odd bit than for all the others, and therefore the tree's output would have a glitch on it in certain cases when the register changed. Is that correct?

If I understand what you are saying, that does sound scary. I presume this is only one example of a pazillion similar problems lurking in the murky darkness, ready to entertain without warning. Some questions:

• Is that something you would learn from a good book, or more likely from experience?
• Would the problem you describe be a problem in a fully synchronous design?
• Would a simulator catch the problem you describe, or would it only show up in an actual implementation?

Please be gentle if one or more of those questions doesn't even make sense. (c:

-- Russ