It takes a long time to learn all of this stuff, and it probably helps to have a background in digital design. I've been doing FPGAs for only about 12 years, and there's always new stuff to learn.



Ah, the reset question. Xilinx FPGAs initialize the storage elements (flops, latches) in two ways. One is with a discrete reset signal, and the other is with the GSR (Global Set/Reset) signal. During configuration, GSR is held asserted, meaning the flops are held in the reset state, and remains so until some time after configuration has completed (that completion is indicated by the assertion of DONE). So you can either yank on your reset input or let the configuration do it.

Which brings up an interesting point. If you include an asynchronous reset for your flops, it turns out that the value to which you reset or preset your flops is actually used as the INIT value for the flop.

So, in the following example, FlopA initializes to 0 and FlopB initializes to 1, either because of the GSR assertion during configuration or because you yanked the reset line:

always @(posedge Clk or negedge Rst_l) begin : Flops
    if (~Rst_l) begin
        FlopA <= 1'b0;
        FlopB <= 1'b1;
    end else begin
        FlopA <= da;
        FlopB <= db;
    end
end // Flops

Prove this to yourself by looking at the fitted design in the FPGA Editor.

So for completeness' sake, I'll designate a master reset signal and bring it to a pin. I typically use active-low resets, so I attach a PULLUP constraint on the reset input pin, which effective keeps the reset deasserted. The FPGA still resets properly because of how things occur after configuration, and I still have a reset signal I can drive during simulation. Plus there's no reason why you can't tie the FPGA reset pin to a micro or something else that can be used to reset it if necessary.

Something interesting you can do is to use a reset supervisor to control the FPGA's PROGRAM signal. The supervisor ensures that the FPGA configuration doesn't start until the power supplies are stable. If there's a power glitch, you don't want to simply reset the FPGA logic as the glitch might have whacked the configuration, so forcing the FPGA to reconfigure in the event of a glitch is a Good Thing.

-a