| ??? 09/21/07 21:29 Read: times |
#144901 - re: Good Catch Responding to: ???'s previous message |
Russ Cooper said:
I also think the example is correct, because it uses what Verilog calls blocking assignments, which are defined to occur in sequential order like in C, and not in parallel like I think you are thinking. I'm still a little bit fuzzy on this, but I think this page explains it fairly well. See my longish response ... PS: The synthesizer seems to implement 'clockDivider' as an array of D flip-flops, and I did notice that it does the assignment to zero by asserting the "clear" input on all the flip-flops rather than clocking in a "real" zero through the D inputs. Maybe this has something to do with why it happens to work with the non-blocking assignments. The synchronous clear is faster and uses less resources than clocking in a zero through D input. Think about it. How would you clock in 0s to sixteen D flip-flops? Answer: you need to put a mux in front of each flop's D input. The comparator output true/false acts as the mux select. One of the mux inputs is the output of the adder (counter outputs through the adder). The other input is zero. When the comparison fails (count != 50000) the flops' inputs are the incremented counter (the flop outputs through the adder). When the comparison fails, the flops' inputs are zero. That mux adds delay to the counter, reducing its maximum frequency. So why construct all of that logic when the synchronous clear is free and exists on all of the device's registers? PPS: I haven't tried either example on the simulator. Maybe it would be more picky somehow and at least give a warning? Nope, it will NOT warn you. Why? Because it's not an error. You really have to know what Verilog does. -a |
