Imagine a breadboard we use to spit on it on this forum, but a big one - maybe the size of a football (oh, sorry, soccer) playground. And, a bag full of SSI/MSI 74's - some of the gates, a 74xx74, maybe a small multiplexer. And an another bag, full of wires of the same size - good just to interconnect closely neighbouring chips. As usual with the breadboard, there are lines running along the columns of chips, this time containing not only power, but also a few privileged signals (clock).

Now, if you want to build a simple project - blinkey, for example - things are relatively straightforward and easy - you put down a few flipflops for a counter, a cascade of 74xx00s for a wide AND to provide the compare level and/or reset value - you can roughly estimate the delays simply by looking into the datasheet of each part.

But, if you want to build something more complex, suddenly you have to start to make crazy things - use a chain of gates just to route a signal out of (or through) an island of other logic, for example. At a certain point, the "crazy" things start to prevail, and the layout starts to be so complex that you are not able to manage it simply using a human brain, and you have to involve a computer. Hence, timing can not be estimated easily anymore, and has to be calculated based on the exact paths.

As I am not actively developing/using FPGAs, this picture might be falsely biased or completely wrong, but, so far, discussing with my friends, this always proved to be roughly valid.

JW