| ??? 09/20/07 20:01 Read: times |
#144843 - re: Have I got this right? Responding to: ???'s previous message |
Russ Cooper said:
Jez said:
If you do something as simple sounding as compare a register to zero, the compiler will probably use an OR gate tree type arrangement which is fine unless your register has an odd number of bits in which case the OR structure then has a static hazard. It things like this which trip people up when they think 'I understand C so I must be able to code in HDL' Okay, let me guess. The problem is that the path through the OR tree could be much shorter for that odd bit than for all the others, and therefore the tree's output would have a glitch on it in certain cases when the register changed. Is that correct? Any time you have different path delays to a combinatorial output, you have the potential for a glitch. Is that something you would learn from a good book, or more likely from experience? Methinks it SHOULD be taught in books, if it isn't. I know that it was clearly pointed out in my digital-design class back in 1986. Once you progress from purely logical descriptions (with zero delay) to actual implementation, delays must be taken into account. Would the problem you describe be a problem in a fully synchronous design? No, because that's one of the reasons one does synchronous design. Consider: if all of the inputs to this wide comparator start at registers, but can take different paths (with different lengths) from their sources, then clearly the output of the comparator can glitch. But if you put a register after the comparator, then all that matters is if the prop delay through the longest path through that comparator meets your clock period constraint. tWould a simulator catch the problem you describe, or would it only show up in an actual implementation? If you simulate using expected prop delays, then yes, the simulator will show combinatorial glitches. A logic-only (zero-delay) simulator may not. Of course that becomes irrelevant in a synchronous design. And there are cases where glitches don't matter in a non-synchronous design. Think of asynchronous SRAMs. For example, as long as you meet the timing requirements on WR\ (data and address line setup and hold) then it doesn't matter if the individual address and data lines have different delays. -a |
