Here's a silly question from somebody who ought to know better. Suppose you have the following circuit, which on the surface looks like a no-brainer:

My old Texas Instruments TTL Data Book for Design Engineers specifies a minimum input hold time of 5 ns for the 74LS74A. For the clock-to-Q propagation delay, it gives a "typical" value of 14 ns, but doesn't specify a minimum propagation delay at all. It seems that you need to guarantee that the clock-to-Q propagation delay is at least as long as the minimum required input hold time in order to be sure the circuit will work reliably.

Am I missing something, or is this circuit really not kosher?

Now the real question: In the land of FPGAs, do the software tools help you avoid problems like this, or at least catch them and point them out? If not, how in the world do you deal with them?

-- Russ