I was talking with a pal about all this yesterday and he said something like "oh, you can write 'for' loops and 'while' loops and everything in Verilog and the synthesizer will just figure it out". That sounds like exactly the kind of thinking that you are warning against. The interesting part is that my pal is a really smart guy, with millions of good ideas, a PhD in Electrical Engineering, thirty years' experience designing mainframe CPUs, a potload of related patents, etc., etc., etc. Could be that he's been a manager long enough that he hasn't actually written any HDL recently, if ever.

Anyway, I think the "think hardware" part will come easily to me. In fact, even when I'm just doing software, I'll sometimes express parts of the design as a hardwarish-looking logic diagram like this one, even though it's going to be implemented in C. For complicated chunks of logic, it sometimes helps me to see it all at once in graphical form like that. Drawings like that also that help me explain things to one hardware-oriented colleague in particular, and they certainly make for cool looking illustrations in otherwise boring design documents.

-- Russ