It's clear enough how to create and use a reset signal in the simulator, but I don't see at all where such a signal comes from in an actual implementation on a real device.

The FPGA data sheet brags that all the flip flops start in a known state at power up, but doesn't say what that known state is or how you would specify it.

The FPGA data sheet talks about a global reset signal that might be what I'm looking for, but sort of hinted that it would be long gone before any of my Verilog started to run.

I searched through the schematic for my eval board and didn't find any sort of reset signal going into the FPGA from the outside. (I could have missed such a thing, however.)

A little blurb here says that in Verilog-2001 you can specify the initial states of your registers at the same time you declare them, but then also goes on to talk about a "local reset" without really explaining where it comes from. And besides, how did it work before Verilog-2001?

Something else I saw I think said you could do it in the .ucf file, but didn't say how.

Bottom line, I'm confused. In something stone simple like this ...

module flip_flop (clk, reset, q, d);

    input  clk, reset, d;
    output q;
    reg    q;
  	  	 
    always @ (posedge clk) begin
        if (reset == 1) begin
	    q <= 0;
	    end
	else begin
	    q <= d;
	    end
	end
  	  	 
    endmodule

... where the heck does 'reset' come from in a real (not simulated) implementation?

-- Russ