| ??? 10/02/07 00:22 Read: times |
#145223 - faucet Responding to: ???'s previous message |
Russ Cooper said:
Do the tools need a special name or something (like your "Rst_1") to identify the reset signal as such, or do they just magically infer it from the structure of the logic? Put another way, if I replace "~Rst_1" in your example with something more complicated like "~Rst_1 && itsTuesday && iLikeTwinkies", will it still initialize the flops as you have described or would that confuse the tools? The tools don't care about names you give to signals. It will (try to) infer the meaning of the signal from the structure of your code. NB: Verilog is case-sensitive, so while Clock and CLOCK are different, only an idiot would use both in the same design. (BTW: VHDL is not case sensitive.) Your expression above will be used to create a reset, but it's worth experimenting and seeing what the tools will do. The FPGA Editor is your friend! As for signal names: I've developed a little "style" over the years. Signals that are active low are suffixed with _l (that's a lower-case L). A signal that is used as a delayed version of another is suffixed with _d. A strobe that is true only on the falling edge of a signal is suffixed with _fe. A strobe that's true only on the rising edge is suffixed with _re. In VHDL, entity (module) ports that are vectors are always written using a type called std_logic_vector but it's often useful to convert/typecast that value into unsigned or signed, so if the port name is MemAddr(7 downto 0) I'll use it an unsigned version of it internally as MemAddr_us because std_logic_vectors cannot be used in arithmetic operations (unless you use the abortion known as std_logic_arith and don't get me started about that). I like to capitalize the first letter of "words" in a signal name, like perhaps PciClk or BitCnt. If a signal is used only in a module (it doesn't appear on the port list), I give it an i prefix (lower case). I never give a clock signal a name that includes its frequency, as it may change! Suppose I'm completely out of pins and I can't afford one for an external reset signal. What would be a good way to either fake a reset signal internally or else change your example so that the flops still get initialized at GSR time? Uh, use a bigger chip. That's sorta half-facetious, as you'll probably need another pin for some other feature or perhaps debug. A less facetious answer: the latest synthesis tools allow you to include an initialization value on a signal when you declare it. So the following: reg foobar = 1'b1; reg [3:0] bletch = 4'b1001;will use the values given as the INIT (power-up reset) values for those signals. Is the magic you've described above guaranteed by the definition of Verilog, or by the synthesis tools, or ... ??? It's how the synthesis tools infer structures from Verilog written to conform with known templates. So, you really DO have to RTFM to see what sort of code you must write to get a specific structure. -a |
