| ??? 09/21/07 00:45 Modified: 09/21/07 00:46 Read: times |
#144854 - Nothing\'s perfect Responding to: ???'s previous message |
Andy Peters said:
Russ Cooper said:
Jez said:
If you do something as simple sounding as compare a register to zero, the ... Would a simulator catch the problem you describe, or would it only show up in an actual implementation? If you simulate using expected prop delays, then yes, the simulator will show combinatorial glitches. A logic-only (zero-delay) simulator may not. Of course that becomes irrelevant in a synchronous design. Unfortunately, it may not simulate the clock routing delays with sufficient precision. That can cause glitches, too. And there are cases where glitches don't matter in a non-synchronous design. Think of asynchronous SRAMs. For example, as long as you meet the timing requirements on WR (data and address line setup and hold) then it doesn't matter if the individual address and data lines have different delays.
-a Nothing's perfect. RE |
