The answer to your question is "neither."

You just fell into the trap of thinking that the Verilog initial statement is (or can be used as) a reset.

It turns out that initial blocks are exactly like always blocks, with one exception: initial blocks run exactly once, whereas once you get to the bottom of an always block, it jumps back to the top (or suspends until a condition in the sensitivity list is met).

Assigning a register or a wire in more than one block is bad form, so the assignment in the initial block competes with the assignment in the always block that implements the counter. Do this in VHDL and you get a nice big warning about assigning to a signal in more than one process. Verilog gives you the rope and says, "Go ahead, hang yourself. See if I care." And what's worse is that the Xilinx tools allow initial blocks and they actually have examples where initial is used to reset state registers!

The other "gotcha" is that the order in which statements in your file are executed is not specified by the Verilog LRM. It might execute the blocks in the order in which they are given in the file, or it might not. So depending on the order of execution in a simulation is a bad thing, although in your case, you lucked out and the tool cleared counter first. If it had not done that, your waveform would have shown a bunch of "X" for the counter value and it would never have updated. To solve this you need a proper reset.

So back to what the synthesizer did. Looks like it got confused by the initial statement and the synchronous clear. It should have barfed on it or at least given you some kind of warning.

-a