Consider this ...

When you, say, assign a value to an output bit when your counter reaches a certain value, having described your hardware behaviorally, the software is at liberty to use a comparator, which potentially is a rather large construct if the counter is long. On the other hand, given that a synchronous counter already has carry stages from one flipflop to the next, decoding a specific value, perhaps into a set-reset flipflop, is just as synchronous, and can be implemented with considerably less logic.

Expressing your logic structurally rather than behaviorally gives you the means to specify how it is implemented. Now, I don't know how it works in Verilog, but it makes considerable difference in VHDL. Often there's a difference in timing vs. a difference in resource utilization that has to be traded off.

There's a preponderance of emphasis on writing VHDL for synthesis, among the published literature, and I doubt it's different for Verilog. Sometimes all you need is a behavioral description, but if you care whether your design efficiently utilizes the hardware that you're buying, you have to consider the low level details. Specifying your hardware in HDL does not isolate you from low-level details as writing MCU code in HLL might do. You must always "think hardware."

RE