??? 09/28/07 05:50 Read: times |
#145048 - OP Update 5 of ? Responding to: ???'s previous message |
I've done a bunch of throw-away experiments with Verilog over the past few days and I think I'm about ready to try something (a lot) more involved than the little counter I was messing with before. A couple of guys here have mentioned a Morse code decoder. That sounds like fun to me, small enough to be doable, yet complicated enough to be challenging. I'd like it to handle input at any reasonable speed, and to automatically track slow changes in speed. RS232 ready for shipment to Hyperterminal or whatever seems like a reasonable way to dispense the output.
Here's a high level block diagram of what I have in mind: I've been using the word mark to mean either a dit or a dah, and space to mean the silent periods between the dits and the dahs. The topmost block in the diagram watches the input line for transitions in either direction. For each one, it spits out the duration of the mark or space just ending (this is just the time since the previous transition), along with a single bit to indicate whether it was a mark or a space. The FIFO in the middle of the diagram buffers the raw event information for use later by the decoder below it. The decoder uses a simple table lookup scheme to translate sequences of dits and dahs into the corresponding ASCII codes. Finally, the block at the bottom serializes the ASCII codes into an RS232 bitstream that something like Hyperterminal can display. But wait! How does the decoder know the difference between the dits and the dahs? Well, everyone knows that dahs are longer than dits, but the decoder needs an actual threshold between the two to sort out the raw event information from the FIFO. The block on the left side of the picture watches the marks as they occur, discriminates the long ones from the short ones, and generates the threshold that the decoder needs. I have a pretty good idea how this threshold detector will work, but I don't have any good pictures of its guts just yet. It may actually be easier to describe it in Verilog than to draw the picture. We'll see. Comments are welcome, as always. -- Russ |