| ??? 10/15/07 19:20 Read: times |
#145776 - Thanks, Jez Responding to: ???'s previous message |
Jez said:
You are looking at the behavioral simulation there which is the idealised version with no propagation delays so events occur instantaneously. What you will find is that you can get your compiler to spit out a post 'place and fit' netlist which has all the delays back annotated into it, its essentially machine generated hdl which you can then plug back into your simulator and you will see that the design then works as you would expect. Good grief. If that's how it works, then what's the value of the behavioral simulation in the first place if it's not expected to behave like real design? And do you have to actually synthesize, place and route the design in order to get the delay information that goes into the back annotated netlist? If so, what do you do about the testbench, which may not be synthesizable? Do you have to manually put the appropriate delays in it? If somehow you don't need to do the place and route to get the delay info, where does the delay info come from? Do the tools just make some assumptions or something? This is turning into a real can of worms. Good thing I'm doing it just for fun and haven't given up my day job. -- Russ |
