| ??? 09/17/07 23:12 Read: times |
#144724 - re: OP Update Responding to: ???'s previous message |
Russ Cooper said:
Every time I reconnect the USB programming cable to my PC, Windows acts all surprised, says "new hardware found", and proceeds to install the same drivers and whatnot that it did two minutes earlier. Somehow this doesn't seem right. That's ... odd. I assume that the cable is always in the same port on the computer. Must be digilent's (or Xilinx') stupid drivers. The original Xilinx "Hi, I'm alive" program must reside in non-volatile memory somewhere, since it's rarin' to go every time the board powers up. When I put my program onto the board, however, it doesn't survive a power down. So I must be missing a step somewhere that's needed to store it into flash. Indeed the original program IS stored somewhere. There's a Xilinx configuration EPROM on the board (look for the wide 20-pin SOIC marked "XCF02..." or "XCF04..."). The FPGAs have a handful of different configuration modes. When the board is powered it, the part configures itself from an on-board EPROM. This is called "master serial" mode. When you configure it using your cable, you are using JTAG mode. I assume you're using the Xilinx iMPACT tool. iMPACT does a lot of things. You can use it to generate a PROM file (usually a .mcs) that is used by an EPROM burner to program the EPROM. You can then use iMPACT to program the EPROM using that file you just generated. Also you can use it to directly configure the EPROM. So unless you actually re-program the EPROM you will always power-up with the default "Hello World!" configuration. There should be a Xilinx doc that explains how to use iMPACT. Sooner or later, I'm going to want to abandon the IDE-like environment that Xilinx provides and move (some would probably say "revert") to a more automatic setup involving "make" or some batch files or something similar. I haven't seen how to do that yet, but I suspect that there must be a collection of commad line programs somewhere that is actually doing all the real work. Yep, the GUI calls a series of programs to do all of the work, and there should be a command log generated. Unfortunately, the Xilinx GUI is stupider than a brick and spews temporary files in your project directory so you'll have to look for it (it has an obvious name). If that's the case, it shouldn't be a big trick to set up batch processing of some sort. It's not a big trick, but it's still a trick. I have a standard Makefile that I use with my FPGA projects, but it depends on some other Xilinx configuration and project files (one for the synthesis, of course the .UCF for constraints, and another file for BitGen). I also set up my projects so that the VHDL sources are NOT in the same directory as the Xilinx project, and you have to tell the ISE to NOT copy your sources to the project directory. Plus there are certain "gotchas" like how XST wants the part number string in a certain format but the back-end tools want it in a slightly-different format. Oh, BTW: I run my makefile in a Cygwin shell rather than in the Windows cmd.exe, because it just works better. But I suppose that while you're learning how to set up the various options (and there's a zillion of 'em), it's best to use the GUI. Just make sure you keep your sources separate from the ISE project directory. One more thing: the fookin' ISE project file is huge and changes every time you open the project (even if you don't change any thing) so putting it into a revision-control system is a non-starter. Good luck. -a |
