| ??? 02/14/11 08:22 Read: times |
#181074 - Horses for courses Responding to: ???'s previous message |
Michael Karas said:
there are aspects (part of) some projects where the specific hardware or instruction set characteristics fit the problem solutions like the very most comfortable glove. Although it has nothing to do with the actual article, this does seem to be very well illustrated by his example: On Stack Overflow, Nigel Jones said:
... code fragment appears below.
void compute_time(uint32_t time)
{
uint32_t days, hours, minutes, seconds;
seconds = time % 60UL;
time /= 60UL;
minutes = time % 60UL;
time /= 60UL;
hours = time % 24UL;
time /= 24UL;
days = time;
}This approach has a nice looking symmetry to it. However, it contained three divisions and three modulus operations. I thus was rather concerned about its performance and so I measured its speed for three different architectures – AVR (8 bit), MSP430 (16 bit), and ARM Cortex (32 bit). In all three cases I used an IAR compiler with full speed optimization. The number of cycles quoted are for for 10 invocations of the test code and include the test harness overhead:
AVR: 29,825 cycles MSP430: 27,019 cycles ARM Cortex: 390 cycles No that isn’t a misprint. The ARM was nearly two orders of magnitude more cycle efficient than the MSP430 and AVR. http://embeddedgurus.com/stack-ove...h-caution/ There will, of course, be plenty of other examples where the roles interchange Michael Karas said:
Knowledge of 3, 4, 5, or even more platforms allows you to find the perfect gloves for any job. |
