The problem is that you, like all overclockers, likely have no background in gate-level digital electronics design, specifically in regards to static timing analysis. Those of us who do FPGAs for a living are VERY aware of its importance.

Basically, the design rules of the silicon dictate prop delays, set-up and hold times and the rest of the usual timing properties. So when a design is complete, you do a static timing analysis on it, which takes into account the worst-case timing parameters, of node voltage, prop delay, etc etc and from this, the maximum guaranteed-to-operate clock frequency falls out.

Keyword above is "guaranteed." The part WILL work in the worst-case conditions at the maximum guaranteed frequency. It may work at higher frequencies. It might not. You don't know. So are you willing to bet your product design and your reputation on a deliberate misuse of the part because in one case it "works?"

That's the problem. Glad you asked.

-a