I haven't seen a Viewlogic schematic since the early '90's, so I can't comment on that, but the major mfg's have schematic capture as an entry option in their own development software suites. The last programmable logic vendor to abandon Viewlogic, IIRC, was Cypress, in about 1993. They allowed its use but didn't provide it as a part of their package.


They provide an entire library of preverified symbols, e.g. adders, MAC's, mux's, decoders, counters, in some cases of arbtirary (parameterized) length or width, etc. An entire function can appear as a single symbol in the schematic, e.g. if you have 12 805x's in the schematic, each one would be a single block, and the block could include the memory and interface logic it uses as well. What underlies the symbol could be a 100-pages of HDL code. That wouldn't necessarily make it easier to review/verify, but it would make it easier to follow on the schematic.

You think you'd have your head around an HDL description of an 805x any sooner? Why, then, do the published IP's that the O/P wanted to consider have, in some cases, multiple compile-time errors per module in both XILINX' and Altera's compiler? How portable is that, when it's claimed it's synthesizable code?

RE