| ??? 11/12/06 18:56 Read: times |
#127827 - salient point Responding to: ???'s previous message |
Richard Erlacher said:
I've got something on my bench now that didn't exist at lunchtime. It's not complicated, but it works and I'm satisfied that it works because I could actually try it with a pair of signal generators to produce the complex waveform that I need to test and an oscilloscope to monitor the four signal lines. It would have taken me longer to write an adequate testbench than it took ot program the logic and put the required buffers on the board. I've highlighted the salient point. Sure, if the circuit is simple enough one can build it and test it on the bench without simulating. But most designs are not trivial and upfront thought about simulation and verification is required. I'd rather simulate a design than spend hours in the lab with a 'scope and logic analyzer trying to figure out which buried internal signal (that I have to bring out to a port pin, which means modifying perhaps several layers of hierarchy) is failing. Xilinx ChipScope is nice, assuming you haven't used up all of the block RAMs in the device. And when you do your design review, do you show them 'scope traces? The test equipment also allows me to do things a simulator like ModelSim has trouble with, like recovering from metastability. I agree, post-route simulations useing back-annotated timing data may sometimes be a problem when you need to synchronize inputs to the FPGA clock. However, I rarely do a post-route simulation; proper constraints and static timing analysis tell you that your functional design will work up to the clock frequency specified. Metastability isn't really a problem; use two synchronizing flip-flops in modern FPGAs and you've reduced metastable events to once in a trillion years. -a |
