| ??? 11/05/06 19:48 Read: times |
#127395 - What are you talking about Responding to: ???'s previous message |
Richard Erlacher said:
If you want information about this board, it's very scanty. There is no schematic, no documentation that's directly applicable to this board at all, and a 2004 (very much outdated) book on programmable logic that may be helpful in using Digilent's pre-2004 boards and XILINX's products of that era. Absolutely Wrong. Schematic (2006 release): http://www.xilinx.com/bvdocs/ip...al_sch.pdf 164 page User Guide: http://www.xilinx.com/bvdocs/userguides/ug230.pdf 17 reference designs: http://www.xilinx.com/products/...esigns.htm Board layout: http://www.xilinx.com/products/...erbers.pdf Richard Erlacher said:
The FPGA boards I have lack sufficient on-board PROM, with one exception, to utilize the FPGA fully. This tendency seems to have been continued. Wrong yet again. The configuration bitstream size for a design is completely independent of the design's complexity for a given FPGA. A design using a single AND gate has the same bitstream size as a design for a vector processor. There is NO way for a design to only partially use an FPGA, the entire configuration must fit in the PROM. Plus you obviously have never used this board since it contains an XC04FS platform flash. Said memory has 4 Mbits of space, while a XC3S500E needs only 2.2 MBits of space to hold its configuration data. Thus this board actually has nearly twice as much configuration memory as it actually needs, and that memory I believe is available to the user as general purpose storage if you specify that the configuration pins become user IO after configuration has completed. Richard Erlacher said:
It uses a rather fragile 100-pin Hirose FX2 plug connector that are incompatible with conventional ribbon cables for purpose of connecting to off-board circuitry. That connector is anything but fragile and is compatible with any standard 0.1" male header. In fact, with a gender bender, this FPGA board becomes pin for pin compatible with both of these expansion boards: http://www.digilentinc.com/Products/...=Accessory http://www.digilentinc.com/Products/...=Accessory Richard Erlacher said:
My kit came with an outdated ISEv8.1 (They're on 8.2 with SP3 by now, and I've only had the board about four months. They don't have the software working right (as well as earlier versions) yet, either.) Irrelevant since this FPGA is supported by Xilinx's free webpack software which provides 99% of the same basic functionality as its $2000 full ISE Foundation counterpart. Richard Erlacher said:
The FPGA boards came with programming cables that adapted the parallel port to the board's JTAG connector. Those cables are awful and should never be used as any nearby noise will cause them to screw up. Only use Xilinx programming cables as they are superior to anything else available (though they cost $150 which is why this board is so great since that $150 circuit is built into the board itself). Richard Erlacher said:
to facilitate operation of the device as a host for MicroBlaze soft-core and running LINUX Who in their right mind runs a LINUX OS on a soft processor core in a 500,000 gate FPGA. Maybe on a much bigger, faster FPGA with built in PowerPCs but not this one. |
