| ??? 11/13/06 21:55 Read: times |
#127908 - schematic verification Responding to: ???'s previous message |
Russ Cooper said:
So if I may guess, what I think you meant to say was, "there's no way you'd be able to convince yourself that the schematic was correct." Is that right? I can believe that you are right, but it would be helpful to understand why. Is it because the schematic would be huge? Or because the logic would be incomprehensible (even if correct) because it was synthesized automatically? Or all of the above? Or something else? If you already had a schematic that implemented the function, presumably you'd just use that, rather than write HDL and synthesize. .. but to answer your questions: yes, all of the above. Because in order to verify that the synthesis tools generated the correct logic, you'd have to pore through the results, and for non-trivial designs, that would take a LOT longer than is reasonable. -a |
