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???
11/13/06 19:57
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#127900 - Yes, but ... and there's always a but ...
Responding to: ???'s previous message
True enough, some folks do understand a map better than a text-only route description. There's more to that, though, and, no, it's not ALL age-related. Two things come into play here.

Consider, for a moment the analogy between a map and a schematic diagram, and schematic diagrams are used in places far outside electronics. If you put the entire map on a single sheet, and just zoom in to the areas of interest, you always have a sense of where you are in the local universe you're exploring. If you have a stack of listing pages, whether HDL or route description, it's a different world. Perish the thought that you'd shuffle the pages in your route description, particularly if it's modular, hence, has discontinuous page numbers.

If you KNOW that everybody can read a map, then the map is generally the best way to tell folks where the picnic is. If you give them a route description, in, say German, then there will be folks who understand it better than others, and the likelihood that everyone will get to the picnic will be diminshed. That's OK so long as the guy with the keg reads and understands German.

Since YOU, Russ, are new to programmable logic, I'm assuming you did learn how to read schematics, at least as superficially as it's taught in undergrad logic circuits courses, and, perhaps, from looking at enough schematics of MCU circuits. It was my thought that getting started would be easier if you didn't have to worry about the multiple power supplies, multiple steps in implementing logic in an FPGA, and multiple years (well maybe if we include the vagaries of the tools) of learning one or another HDL before you can be sufficiently CONFIDENT that your logic will work as you planned.

If you'd rather learn to do things in one HDL or another, that's not my concern, though you won't be welcome around here if you can't express your logic in symbolic form as well.

My emphasis is not on how the logic is to be entered, but on how it is to be presented for analysis and review. The guys who pay for logic design want to be assured that they're getting what they want. Many of them have never learned anything about HDL's, since they were busy building a successful business. They did learn to read schematic diagrams, whether they were trained as Electrical, Civil, Mechanical, Chemical, or Nuclear engineers. It's THAT level of presentation that matters. The symbols can have underlying HDL descriptions, but the presentation should be in a form with which the reviewers are comfortable.

Some people are uncomfortable with reviews. They prefer to obfuscate their work in "clever" 'C' code or esoteric HDL expression. Perhaps it's because they haven't done all the groundwork and lack confidence in what they've delivered. I have on sympathy for them. I implore you not to become one.

RE

List of 81 messages in thread
TopicAuthorDate
Getting Started With FPGAs            01/01/70 00:00      
   A Book            01/01/70 00:00      
   Proceed with caution!            01/01/70 00:00      
   This is quite a nice deveolpment board            01/01/70 00:00      
   I like this board            01/01/70 00:00      
      I\'ve got one of these and can\'t recommend it            01/01/70 00:00      
         What are you talking about            01/01/70 00:00      
            Let me explain ...            01/01/70 00:00      
   generaly speaking            01/01/70 00:00      
      Damn, Jez, you need a spell-checker!            01/01/70 00:00      
         HDL-based design needs TEST BENCHES            01/01/70 00:00      
            I use 'em all the time, but ...            01/01/70 00:00      
               If your design is so simple            01/01/70 00:00      
                  What\'s important is the entry effort            01/01/70 00:00      
                     I dunno where you get these ideas from Richard            01/01/70 00:00      
                        Can you say ModelSim?            01/01/70 00:00      
                     Wrong            01/01/70 00:00      
                        Well, the schematic needs a little work            01/01/70 00:00      
                           more work?            01/01/70 00:00      
                              a few points ...            01/01/70 00:00      
                           ...            01/01/70 00:00      
                     HDL vs Schematics, take 1E6            01/01/70 00:00      
                        Thta may be great comfort to you ...            01/01/70 00:00      
                           Schematics? You're kidding!            01/01/70 00:00      
                              No, nor is my customer.            01/01/70 00:00      
                              both are a 'representation of Boole'            01/01/70 00:00      
                                 Yep, you're right...            01/01/70 00:00      
                                    To Clarify            01/01/70 00:00      
                                       schematic as equivalence check            01/01/70 00:00      
                                          Manual verification impossible because ...            01/01/70 00:00      
                                             schematic verification            01/01/70 00:00      
                                       Some more clarification            01/01/70 00:00      
                                          hanging problem            01/01/70 00:00      
                                             so will your post be            01/01/70 00:00      
                                    it's not fear of the unknown, but fear of its cost            01/01/70 00:00      
                           Static Timing Analysis and those "young engineers"            01/01/70 00:00      
                              It's a sign of the times, I suppose            01/01/70 00:00      
                                 And times change            01/01/70 00:00      
                                 senior?            01/01/70 00:00      
                                    That's because you've been avoiding the subject            01/01/70 00:00      
            I agree entirely. test benches are a pain but            01/01/70 00:00      
   Update from the OP            01/01/70 00:00      
      It's true ... we see things differently            01/01/70 00:00      
      the first buuk for any such venture            01/01/70 00:00      
      FPGA boards and that Cypress book            01/01/70 00:00      
         This may answer your question(s)            01/01/70 00:00      
   some of the references in the fpga faq            01/01/70 00:00      
      Good attitude            01/01/70 00:00      
   Also remeber to look at webistes like www.xilinx.c            01/01/70 00:00      
   My recommendation and opinions            01/01/70 00:00      
      I would stay away from Virtex-II            01/01/70 00:00      
         If you're going to fiddle with the 805x core ...            01/01/70 00:00      
            Something about life-cycles            01/01/70 00:00      
               No doubt about it.            01/01/70 00:00      
                  useful work            01/01/70 00:00      
                     Well, I beg to differ.            01/01/70 00:00      
                        salient point            01/01/70 00:00      
                           There's an area where that's not necessarily true            01/01/70 00:00      
                           FPGA Editor            01/01/70 00:00      
            Not necessarily            01/01/70 00:00      
               It's still too costly            01/01/70 00:00      
   Thanks to all            01/01/70 00:00      
   Update #2 from the OP            01/01/70 00:00      
   A testbench is...            01/01/70 00:00      
      I C            01/01/70 00:00      
         test bench            01/01/70 00:00      
            Makes sense            01/01/70 00:00      
   Yeah but...            01/01/70 00:00      
   Tristate buffer with propagation delays            01/01/70 00:00      
   Schematics vs. HDL            01/01/70 00:00      
      In a nutshell            01/01/70 00:00      
         it\'s been a while            01/01/70 00:00      
      Yes, but ... and there's always a but ...            01/01/70 00:00      
   Yep you can its called gate level design            01/01/70 00:00      
   Its really nothing to do with showing off            01/01/70 00:00      
      did you paraphrase this?            01/01/70 00:00      
      Jez, It\'s not \"sea of gates\" design, you know ...            01/01/70 00:00      
         Richards, it is there philosophy            01/01/70 00:00      
         Viewlogic            01/01/70 00:00      
   it is true            01/01/70 00:00      
   Here you go Richard graphical design exploration            01/01/70 00:00      

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