In communication circuitry where everybody is working from their own crystal oscillator, particularly if they're all thinking they're very close to the "true" value, within, say, 50 ppm. When that is the case, and you're switching between inputs, each of which is generated from its own version of, say, 20 MHz give or take those 50 ppm, if the edges come very close to one another, the dual-rank registers may not save you within the length of a packet of data. Dual rank registers seem to save you when two signals are very close to one another, causing setup/hold time violations rarely, but if they're cause on every clock/data relationship for a long period, you're in trouble.

There, it becomes important to be able to simulate the post-fit or post-route performance, just to demonstrate that your circuitry can cope with rapidly and frequently repeated violations.

FPGA's have clock synchronization facilitators, either DLL's or PLL's, that help with deskewing. However, they don't help much with synchronizing the internal clock with an external one, particularly if that external one changes frequently. The result is that you have to devise synchronization tools that are particularly subject to metastability. Circuitry can recover from metastability. The simulators don't seem to have learned that yet.

Comparing simulated results with physical results, by providing logic analyzer or even oscilloscope displays is useful for assuring customers that what was predicted by the simulator is what is most likely to happen. It's all a mattter of statistics, of course, but it does happen that things pop up in the "real" world that don't in the simulator.

It's not part of the design review, at least not the critical review prior to acceptance and delivery, but the correlation between simulation and performance of every device to be delivered is demonstrated in advance of final review. It's done by capturing the display and showing it in correspondence with the simulation. This provides, at least, the statement that it does appear to work as it's designed to work. It's better than just behavioral or functional simulation.

Unfortunately, simulators have a problem with real-world events such as occur when the leading edge of signal A has, for some time preceded the leading edge of signal B, but the two come closer and closer to coincidence, and, ultimately, their roles are reversed. Metastability often occurs in just those circumstances. Simulators have trouble with that (a) because it requires very gradual incrementation of the decreasing phase differences, which implies REALLY long runs, and (b) simulators have trouble predicting the behavior of signals that undergo metastabile outputs/inputs. Even SPICE has trouble with 'em.

RE