remembering that VHDL is a design description language and a simulation language a testbench is a simulation of some external component or collection of components which your design would plug into in the real world.If you had written a VHDL processor and you wanted to test that it worked correctly when connected to some RAM and ROM then your testbench would consist of a VHDL model of the RAM and ROM and the connections from your design (the device under test) and you would use some simulator to examine the behavour of the testbench to see if it worked as you planned.This is where the parts of VHDL which cannot be synthesised come into play because there is no need for the model of the RAM or ROM to be synthesisable you can write those part using whatever is easiest with worrying about how they could be made in real life.Typicaly the testbench reads files containing the test sequences to be applies to the device under test and records the results.
Mostly testbenches come into their own when you are working an a very large project and how much time you spend on getting the testbench right depends on how much it costs to correct any erros when the device is out in the field.Sometimes for small projects the testbench is very simple for large protects the testbench can be hugely complex.
Of course there is the question of how do you know that the testbench is correct, but if you worry about that then you tend to dissapear up your own specification.
There are software tools which use methods of formal verification but they are seriously expensive and only ever used for ASIC design.