First of all, BUFFER is a representation of <output register with feedback>. That's what one uses to build counters. Unfortunately, it doesn't work in some VHDL compilers as implemented by component vendors despite the fact that it's EXACTLY the physical construct that's wanted. One unfortunate side effect of this is that more hardware resources are needed in order to implement certain constructs. In an FPGA, the number of registers is often totally irrelevant, since the utilization of the resources in the device seldom rises to levels above 60%. However, CPLD's, the macrocells of which are, in fact output registers with feedback, are register-poor, so you want to be able to use them. While it was straightforward enough to implement the equivalent of the old 74BCT2424 in a 24 macrocell CPLD back when it was done via vendor-specific HDL's, it's not reliably implementable in current VHDL or Verilog because the tools no longer emphasise precise specification of the hardware implementation. The result is that one has to use 48 macrocells just to get the function one previously had in 24. This increases the required package size, and also the device cost. I guess the vendors like that, but it's irrelevant since they don't make those components any longer, nor do they use the packages to which this issue once applied. The newer tools, however, don't implement logic as efficiently as the old ones once did. I guess that's progress.

Then ... the argument over whether HDL or schematics is "better" depends too much on how you're going to use the documentation. HDL, after all, a specification tool. If my customer wants meaningful schematics, then I have to give them to him. What's sad is that CAE tools, particularly those from programmable logic vendors, have increasingly poor schematic entry tools with every release. It's not that they don't spend money on development or maintenance, but that they pay less and less attention to testing. The result is that you are alowed to spend time setting up the schematic environment, only to have the schematic tool force you to abandon and reinstall the setup becuase it lost the context, due to poor context tracking,which means I have to exit from the ISE, for example, and restart it, not losing any work, but losing lots of time becuase now I have redo the setup.

It's true, in a generation or so, nobody will even remember what a logic symbol was, or how it was used to represent what logic was needed, as HLL compilers will do it all for us, designing the processor, the memory, the interfaces between them, and everything else. What worries me is, "who will ensure that's being done RIGHT?"

RE