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???
11/12/06 23:46
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#127836 - No, nor is my customer.
Responding to: ???'s previous message
Roger Steiner said:

Implementing something in HDL doen't imply that the documentation or better the specifiaction has to be in the same language. For my own project as well as for contract work all those documents had some block diagrams explaining the system with as much detail to not confuse the reader or leave some space for the actual implementation. Your civil engineer would think of footwear when reading about flip-flops.
code reviews are done by people how know the language or system in which it is implemented. It's useful to have more than one HDL guy in a project. The rules are the same as with software.

A schematic doesn't necessarily represent every circuit element as a bunch of gates or simple flipflops. It's much easier for that civil engineer, over 50, (who, BTW, was required, as an undergraduate, to take a logic circuits course as well as a basic electronics course ... resistors, cap's, Thevenin, Norton, LaPlace, phasors ... etc.) can read a logic diagram just fine, and, in fact, better than most coders under 35, to my experience, since he was taught the difference between a J-K and a D flipflop. If he's the guy in charge of the project, probably because of the stake he holds in the company, he's concerned with the overall function, with details that might have "fallen through the cracks," and things of that sort. He wants to be assured that what he's being sold is what will be delivered. If you enter the entire design in HDL and then let him review a schematic, that certainly doesn't precisely reflect what he's being sold. If he's asked that he be allowed to review what's being delivered, you have to give him what he's asked for. If he wants schematics, you have to use 'em, else he'll find someone who'll do that.

Schematic entry can be useful to quickly glue some components together for a test, but thats it, anything else go HDL, Andy already said why, and i second his opinion.
Besides that, schematic entry tends to lead less experienced users to some awful constructs.

Cheers, Roger


I agree, it's useful for up to, maybe, 250 circuit blocks, whether they're library components, IP blocks, or state machines. The problem is with the software and not with the concept. The latest software set from XILINX has some real issues. Take a look for yourself.

RE





List of 81 messages in thread
TopicAuthorDate
Getting Started With FPGAs            01/01/70 00:00      
   A Book            01/01/70 00:00      
   Proceed with caution!            01/01/70 00:00      
   This is quite a nice deveolpment board            01/01/70 00:00      
   I like this board            01/01/70 00:00      
      I\'ve got one of these and can\'t recommend it            01/01/70 00:00      
         What are you talking about            01/01/70 00:00      
            Let me explain ...            01/01/70 00:00      
   generaly speaking            01/01/70 00:00      
      Damn, Jez, you need a spell-checker!            01/01/70 00:00      
         HDL-based design needs TEST BENCHES            01/01/70 00:00      
            I use 'em all the time, but ...            01/01/70 00:00      
               If your design is so simple            01/01/70 00:00      
                  What\'s important is the entry effort            01/01/70 00:00      
                     I dunno where you get these ideas from Richard            01/01/70 00:00      
                        Can you say ModelSim?            01/01/70 00:00      
                     Wrong            01/01/70 00:00      
                        Well, the schematic needs a little work            01/01/70 00:00      
                           more work?            01/01/70 00:00      
                              a few points ...            01/01/70 00:00      
                           ...            01/01/70 00:00      
                     HDL vs Schematics, take 1E6            01/01/70 00:00      
                        Thta may be great comfort to you ...            01/01/70 00:00      
                           Schematics? You're kidding!            01/01/70 00:00      
                              No, nor is my customer.            01/01/70 00:00      
                              both are a 'representation of Boole'            01/01/70 00:00      
                                 Yep, you're right...            01/01/70 00:00      
                                    To Clarify            01/01/70 00:00      
                                       schematic as equivalence check            01/01/70 00:00      
                                          Manual verification impossible because ...            01/01/70 00:00      
                                             schematic verification            01/01/70 00:00      
                                       Some more clarification            01/01/70 00:00      
                                          hanging problem            01/01/70 00:00      
                                             so will your post be            01/01/70 00:00      
                                    it's not fear of the unknown, but fear of its cost            01/01/70 00:00      
                           Static Timing Analysis and those "young engineers"            01/01/70 00:00      
                              It's a sign of the times, I suppose            01/01/70 00:00      
                                 And times change            01/01/70 00:00      
                                 senior?            01/01/70 00:00      
                                    That's because you've been avoiding the subject            01/01/70 00:00      
            I agree entirely. test benches are a pain but            01/01/70 00:00      
   Update from the OP            01/01/70 00:00      
      It's true ... we see things differently            01/01/70 00:00      
      the first buuk for any such venture            01/01/70 00:00      
      FPGA boards and that Cypress book            01/01/70 00:00      
         This may answer your question(s)            01/01/70 00:00      
   some of the references in the fpga faq            01/01/70 00:00      
      Good attitude            01/01/70 00:00      
   Also remeber to look at webistes like www.xilinx.c            01/01/70 00:00      
   My recommendation and opinions            01/01/70 00:00      
      I would stay away from Virtex-II            01/01/70 00:00      
         If you're going to fiddle with the 805x core ...            01/01/70 00:00      
            Something about life-cycles            01/01/70 00:00      
               No doubt about it.            01/01/70 00:00      
                  useful work            01/01/70 00:00      
                     Well, I beg to differ.            01/01/70 00:00      
                        salient point            01/01/70 00:00      
                           There's an area where that's not necessarily true            01/01/70 00:00      
                           FPGA Editor            01/01/70 00:00      
            Not necessarily            01/01/70 00:00      
               It's still too costly            01/01/70 00:00      
   Thanks to all            01/01/70 00:00      
   Update #2 from the OP            01/01/70 00:00      
   A testbench is...            01/01/70 00:00      
      I C            01/01/70 00:00      
         test bench            01/01/70 00:00      
            Makes sense            01/01/70 00:00      
   Yeah but...            01/01/70 00:00      
   Tristate buffer with propagation delays            01/01/70 00:00      
   Schematics vs. HDL            01/01/70 00:00      
      In a nutshell            01/01/70 00:00      
         it\'s been a while            01/01/70 00:00      
      Yes, but ... and there's always a but ...            01/01/70 00:00      
   Yep you can its called gate level design            01/01/70 00:00      
   Its really nothing to do with showing off            01/01/70 00:00      
      did you paraphrase this?            01/01/70 00:00      
      Jez, It\'s not \"sea of gates\" design, you know ...            01/01/70 00:00      
         Richards, it is there philosophy            01/01/70 00:00      
         Viewlogic            01/01/70 00:00      
   it is true            01/01/70 00:00      
   Here you go Richard graphical design exploration            01/01/70 00:00      

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