| ??? 11/10/06 22:35 Read: times |
#127749 - HDL-based design needs TEST BENCHES Responding to: ???'s previous message |
Richard Erlacher said:
Most of my clients object to the use of HDL's becuase it means they have to hire multiple consultants to help in reviews and translations of the design specification into something they can understand.
A review of a 100-page HDL listing takes two months, and, if you have N HDL "experts" you get N+1 opinions about what it says. OTOH, nearly anybody can read and interpret a 1-sheet schematic which is what that 100-pages of HDL represents, and a review of that takes an hour at most, requiring no outside people, aside from me. So none of your code reviewers ask for a complete test bench that can be used to verify the code? Only an idiot would spend time reading the code ... really. A proper test bench will fully exercise the design. Of course, this requires engineering time to create the test bench, which should be more than the "drive the bus and toggle the clock" you'd do with CUPL. I have a fairly large library of bus-functional models that I use as components in my test benches. It's pretty cool when your FPGA sits between a microprocessor and a peripheral, and you've got models of the micro's bus and the peripheral and the bus transactions are exactly what you'd see on a logic analyzer. -a |
