??? 11/11/06 18:48 Modified: 11/11/06 18:49 Read: times |
#127787 - What\'s important is the entry effort Responding to: ???'s previous message |
A typical ~100-component one-sheet schematic takes hundreds and hundreds of pages of HDL just to describe it. Saving trees is a sufficient justifcation for using the schematic. That doesn't mean the design is idiotically simple.
The fact that anyone who went to engineering school when one had to be able to read, write, and spell, can read and correctly interpret schematics, while that it takes a roomful of HDL experts weeks just to agree on what a page of HDL says, is also sufficient justification. If the typical HDL user knew how much more efficient his design entry would be if he simply put in a symbol for the element he had to type up for half a day, he'd go back to schematics. My main interest in continuing to use schematic entry is in making the review process accessible to the people who pay for it. Any engineer, even mechanical or civil engineers, can easily understand and interpret schematic diagrams, while HDL experts have difficulty even in interpreting their own work once they've been away from it a week or longer. Reviews of HDL-entered designs take weeks and cost hundreds of thousands of dollars, while schematic reviews of the same circuitry (we've tested this notion) take half a day and cost a couple of thousand if one includes the price of lunch. It's unacceptable to enter a design in HDL and subsequently translate it to understandable schematics for review, as it means the client reviews/accepts one thing and pays for another. If there were sufficiently reliable and useful tools to automate the translation, perhaps that would make the process acceptable, but, for now, it isn't. I sometimes use VHDL to enter what becomes a block symbol in a schematic. However, that requires that I provide an extensive device-specific simulation of the HDL-entered logic and additional documentation that specifies and verifies what the functional block is designed to do. Even when the blocks are defined in HDL, in order to present a reviewable block diagram, one has to have a schematic entry package that enables one to document what's "in there" so the senior engineering managers can see what they're buying. RE |