| ??? 11/12/06 06:25 Read: times |
#127807 - Can you say ModelSim? Responding to: ???'s previous message |
Jez Smith said:
Richard you seem to have some very odd ideas about the review process when it comes to VHDL nobody reads through pages of code.
They probably don't read through the software listings either. The ideas I have come from sitting through plenty of reviews, often as the guest-of-honor, having to defend the design, and the outsiders are there to attack it. All they do is if its a large company they get contractors in to write testbenches to the design specification while the actual code for the device is still being written.
That's not the way I see it being done. Most of them require that the testbenches be presented as part of the finished design. The test spec's are presented and we provide the corresponding testbenches. Timing diagrams generated by the simulator provide assurance that the spec's are met, and the simulation timing diagrams also provide assurance that the design criteria are met. If its a small design then the person who wrote the design will probably write the testbench. The testbench tests the design, if the testbench passes then the design is correct. I dont know why you should think that people dont agree on the functionality there are numerous standards IEEE 1164 being the main one which defines all of VHDL, there maybe some confusion about perhaps one or two definitions in pathologicaly obstruse circumstances. It's people who work with schematics who have the problems because you cannot write a testbench to test a schematic. If your customers dont understand that you cannot prove a design using a schematic then thats their problem. How the hell do you test a schematic to see if it meets the timing requirements? I don't know why you believe that, Jez. Native simulators from XILINX and Altera, and Modelsim seem all to work just fine. The software package netlists and translates the schematics into structural VHDL which then can be very thoroughly timing-simulated with incremental changes in clock rates and other details controlled within the testbench in order to find weaknesses and sensitivites. Fault simulation is also generally a requirement. RE |
