First of all, the convention with schematics is to use proven library components. That way one doesn't have to prove the counter works, as it's a part of the software package that implements it.

Secondly, if one of my guys drew this schematic, I'd fire him and get a high-school student who knew that inputs belong on the left and outputs on the right. That's been accepted practice for about two decades.

Thirdly, the correct way to draw a synchronous counter is with 'T' flops, not with 'D' flops, since they needlessly clutter the drawing. That would remove the XOR's and the inverter. A global enable and a reset would probably be a good thing, too. 'D' flops are OK in ripple counters ...

The description of the count process is but a small part of the counter. You have to define the "count" as a signal and, outside the process, transfer the "count" to a STD_LOGIC_VECTOR, since XILINX, among others, doesn't support BUFFER mode. Of course, you'd have to support the enable and the reset, wouldn't you?

RE