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11/04/06 22:21
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#127375 - Proceed with caution!
Responding to: ???'s previous message
Russ Cooper said:
Here are some questions for Jez and/or anybody else who knows what's up with FPGAs.

I understand the concept, but have never messed with an FPGA myself. I would like to remedy that sorry situation by actually getting my hands dirty playing with some sort of evaluation kit. After a brief Google search, I realized that I am too stupid to select one. Hence this note. Can you recommend an evaluation kit that would be appropriate for a complete beginner? At first, I would be happy to do something really, really simple like string together a few gates and flip-flops to make a counter or something. Eventually I would like something capable enough that I could grab one of those free 8051 cores and connect my gates and flip-flops to its I/O lines. I don't want some bleeding edge thing where I will run into problems with the vendor's software or the hardware platform itself. (I will make enough mistakes of my own.) Low cost would be nice. Good documentation would be nice. Some sort of flash-based, download-and-go setup would be nice. How do I decide between Verilog and VHDL? How much money am I talking about here to get started? Supposing I did get to the point of messing with an 8051 core, how does the 8051's program get loaded into its program memory? Does that happen at the same time the FPGA itself is configured? Once a guy's figured out the chips and software from one FPGA vendor, how difficult is it to switch to another vendor's chips and software? Would that be sort of like trying to work with a PIC (*barf*) after having become an 8051 expert? Easier? Harder? In other words, how much of a commitment am I making with my initial selection of a learning environment? What questions have I failed to ask because I'm still too stupid to ask them? -- Russ


Though you may not want to do it, it's a good thing to become familiar with and fluent in CPLD's before FPGA's. They're quicker and easier to implement, cost less, and come in packages you can actually use. A schematic can easily be implemented in a CPLD. All such bets are off where FPGA's are concerned. There are many things you can't easily accomplish in CPLD that become quite straightforward in FPGA. Moreover, you can often enhance the capabilities of an FPGA implementation with a little CPLD outside. In CPLD's, you have lots of logic associated with every flipflop, i.e. they're logic-rich and register-poor. FPGA's OTOH, are logic-poor, in a sense, yet register-rich. Pinouts in CPLD's are essentially fixed, at least after the first time you fit a design, and timing is deterministic. Pinouts in FPGA's often have to be changed in order to accomodate timing constraints, and rerouting often forces pinout changes. Wide gates in FPGA tend to end up being relatively slow because they're built with concatenated lookup tables. That requires addded routing delays, though they're short. There's a lot you can learn by playing with these, but if you want to get a job done today, FPGA may not be the best way.

As for the 8051 core and an evaluation board that might suit your purpose, what you'll want is a kit that has as little on it, asside from the FPGA, a boot PROM, and maybe a level shifter for serial comm's, as possible, but with an FPGA that has enough block RAM so you don't have to attach an external ROM. In that case, you won't need a prototyping area either, though I'd look for a board that has a HUGE FPGA (that's the only way to have at least 64KB of code space and 64KB of XRAM space, in addition to the 256 bytes of internal RAM for the 805x. Just make sure that the software you intend to use has the ability to develop/program the FPGA you use.

Development/evaluation boards tend to have too much rubbish on them, and, most of the time, that rubbish can't be disconnected from the FPGA, so you can't practically use those pins. In fact, most evaluation products are completely useless for anything practical at all. They have "stuff" on them that serves no useful purpose, yet they have no means for "getting rid of it" such as jumpered connections. Many boards have SDRAM and FLASH on board, yet have no means for using it, and, if you do manage to use, say, the SDRAM, you have lots of memory, but no internal resources with remaining with which you can use it.

If 805x-core development is all you hope to do, then you needn't be too fussy, but if you also want to mess with NIOS or MicroBlaze, for example, you need about 8 MB of FLASH and 16MB of external SDRAM for purposes of being able to run an OS. Don't expect anything useful from the "VGA" ports some boards offer, unless you're developing a graphics adapter. Unless they have a 3-color DAC on board, VGA is a pipe-dream. Some of them contain PS/2 connectors. Unless you know you're going to need that, stay away from those boards, as they, again, interfere with useful things for which you might use them.

If possible, try to get a board with no displays, no LCD, no switches, etc, unless they can be removed with jumpers and have the signals routed to a connector by means of which YOU can route the signals to a prototype area. I emphasize this because many boards have costly, fragile, and difficult-to-use connectors that you have to buy in hundreds and have to wait a long time to receive them.

If the board you decide you want has a connector, be sure to order the prototype board that mates with it right away. You never know when they'll suddenly become unavailable.

If you buy a board that's sold by XILINX but made by Digilent, then it's sometimes better to buy it from XILINX because they provide things that Digilent doesn't. Read the fine print! Be sure the features you expect are actually included and installed. Carefully examine the documentation. Often it's incomplete. If it's incomplete, it will likely stay that way.

Forewarned is forearmed.

RE




List of 81 messages in thread
TopicAuthorDate
Getting Started With FPGAs            01/01/70 00:00      
   A Book            01/01/70 00:00      
   Proceed with caution!            01/01/70 00:00      
   This is quite a nice deveolpment board            01/01/70 00:00      
   I like this board            01/01/70 00:00      
      I\'ve got one of these and can\'t recommend it            01/01/70 00:00      
         What are you talking about            01/01/70 00:00      
            Let me explain ...            01/01/70 00:00      
   generaly speaking            01/01/70 00:00      
      Damn, Jez, you need a spell-checker!            01/01/70 00:00      
         HDL-based design needs TEST BENCHES            01/01/70 00:00      
            I use 'em all the time, but ...            01/01/70 00:00      
               If your design is so simple            01/01/70 00:00      
                  What\'s important is the entry effort            01/01/70 00:00      
                     I dunno where you get these ideas from Richard            01/01/70 00:00      
                        Can you say ModelSim?            01/01/70 00:00      
                     Wrong            01/01/70 00:00      
                        Well, the schematic needs a little work            01/01/70 00:00      
                           more work?            01/01/70 00:00      
                              a few points ...            01/01/70 00:00      
                           ...            01/01/70 00:00      
                     HDL vs Schematics, take 1E6            01/01/70 00:00      
                        Thta may be great comfort to you ...            01/01/70 00:00      
                           Schematics? You're kidding!            01/01/70 00:00      
                              No, nor is my customer.            01/01/70 00:00      
                              both are a 'representation of Boole'            01/01/70 00:00      
                                 Yep, you're right...            01/01/70 00:00      
                                    To Clarify            01/01/70 00:00      
                                       schematic as equivalence check            01/01/70 00:00      
                                          Manual verification impossible because ...            01/01/70 00:00      
                                             schematic verification            01/01/70 00:00      
                                       Some more clarification            01/01/70 00:00      
                                          hanging problem            01/01/70 00:00      
                                             so will your post be            01/01/70 00:00      
                                    it's not fear of the unknown, but fear of its cost            01/01/70 00:00      
                           Static Timing Analysis and those "young engineers"            01/01/70 00:00      
                              It's a sign of the times, I suppose            01/01/70 00:00      
                                 And times change            01/01/70 00:00      
                                 senior?            01/01/70 00:00      
                                    That's because you've been avoiding the subject            01/01/70 00:00      
            I agree entirely. test benches are a pain but            01/01/70 00:00      
   Update from the OP            01/01/70 00:00      
      It's true ... we see things differently            01/01/70 00:00      
      the first buuk for any such venture            01/01/70 00:00      
      FPGA boards and that Cypress book            01/01/70 00:00      
         This may answer your question(s)            01/01/70 00:00      
   some of the references in the fpga faq            01/01/70 00:00      
      Good attitude            01/01/70 00:00      
   Also remeber to look at webistes like www.xilinx.c            01/01/70 00:00      
   My recommendation and opinions            01/01/70 00:00      
      I would stay away from Virtex-II            01/01/70 00:00      
         If you're going to fiddle with the 805x core ...            01/01/70 00:00      
            Something about life-cycles            01/01/70 00:00      
               No doubt about it.            01/01/70 00:00      
                  useful work            01/01/70 00:00      
                     Well, I beg to differ.            01/01/70 00:00      
                        salient point            01/01/70 00:00      
                           There's an area where that's not necessarily true            01/01/70 00:00      
                           FPGA Editor            01/01/70 00:00      
            Not necessarily            01/01/70 00:00      
               It's still too costly            01/01/70 00:00      
   Thanks to all            01/01/70 00:00      
   Update #2 from the OP            01/01/70 00:00      
   A testbench is...            01/01/70 00:00      
      I C            01/01/70 00:00      
         test bench            01/01/70 00:00      
            Makes sense            01/01/70 00:00      
   Yeah but...            01/01/70 00:00      
   Tristate buffer with propagation delays            01/01/70 00:00      
   Schematics vs. HDL            01/01/70 00:00      
      In a nutshell            01/01/70 00:00      
         it\'s been a while            01/01/70 00:00      
      Yes, but ... and there's always a but ...            01/01/70 00:00      
   Yep you can its called gate level design            01/01/70 00:00      
   Its really nothing to do with showing off            01/01/70 00:00      
      did you paraphrase this?            01/01/70 00:00      
      Jez, It\'s not \"sea of gates\" design, you know ...            01/01/70 00:00      
         Richards, it is there philosophy            01/01/70 00:00      
         Viewlogic            01/01/70 00:00      
   it is true            01/01/70 00:00      
   Here you go Richard graphical design exploration            01/01/70 00:00      

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