Richard you seem to have some very odd ideas about the review process when it comes to VHDL nobody reads through pages of code.All they do is if its a large company they get contractors in to write testbenches to the design specification while the actual code for the device is still being written.If its a small design then the person who wrote the design will probably write the testbench.The testbench tests the design, if the testbench passes then the design is correct.I dont know why you should think that people dont agree on the functionality there are numerous standards IEEE 1164 being the main one which defines all of VHDL, there maybe some confusion about perhaps one or two definitions in pathologicaly obstruse circumstances .Its people who work with schematics who have the problems because you cannot write a testbench to test a schematic.If your customers dont understand that you cannot prove a design using a schematic then thats their problem.How the hell do you test a schematic to see if it meets the timing requirements?