??? 11/13/06 02:34 Read: times |
#127842 - I C Responding to: ???'s previous message |
Jez said:
Remembering that VHDL is both a design description language and a simulation language, a testbench is a simulation of some external component or collection of components which your design would plug into in the real world. Thanks, Jez. I think that's what I thought. When programming in C, if I write a function like this: int Add(int a, int b) { return a + b; }then I can also write a throw-away function like this to test Add() in isolation from all the rest of my functions: void main() { printf("3 + 5 = %d\n", Add(3, 5)); }If I understand you correctly, this second function is vaguely equivalent to your "test bench", and by the time I finally get it to print out "3 + 5 = 8", I have a fair degree of confidence that both the test bench and the function under test (FUT) are correct. Correct? -- Russ |