??? 11/06/06 00:25 Read: times |
#127410 - Damn, Jez, you need a spell-checker! Responding to: ???'s previous message |
Most of my clients object to the use of HDL's becuase it means they have to hire multiple consultants to help in reviews and translations of the design specification into something they can understand.
A review of a 100-page HDL listing takes two months, and, if you have N HDL "experts" you get N+1 opinions about what it says. OTOH, nearly anybody can read and interpret a 1-sheet schematic which is what that 100-pages of HDL represents, and a review of that takes an hour at most, requiring no outside people, aside from me. When we old-timers were in college, there was no VHSIC standard, so there was no VHDL. There was no Verilog, either. In fact, there weren't even any PAL's. A flipflop was a daghterboard that plugged into a main board, that, in turn, plugged into a backplane. We all seem to understand one another. You young whippersnappers with your HDL's haven't yet solved the problem of translating a huge volume of code into a sheet of block-diagram/schematic. Moreover, the schematic-capture software that XILINX has put in front of us doesn't work worth a &^%$#@! It loses its point of reference in the context and forces you to undo all your confiuration 25 times an hour. When you draw a line, you lose your symbol menus, and when you "check schematic" you lose the entire schematic and have to exit from ISE in order to recover it. I know HDL is the coming, no ... it's already here, thing. However, if you want to draw a block diagram that the entire team can understand without having to go back to school and learn another language, you have to have a tool that enables you to draw a block diagram and make the logical-to-physical mappings that make the thing "real." Yes, testbenching is a big part of the job, and I always use VHDL to generate those. The reason I can get by with this is that it produces a graphic that I can present and everyone can understand. However, if I present an HDL listing nobody can understand that, and if I provide a schematic representation of the logic but generate the programming file from HDL, then I'm asking them to review and accept something on faith. While I've known these people for a long time, and they proably trust me more than they should, not from ethical considerations but from practical ones, they're failing in their fiduciary responsibilities if they let me do that. We have to review what's being bought. RE |