Okay, but I was assuming that the tools would automatically generate a schematic that was guaranteed to be equivalent to the HDL code. Then you'd inspect the schematic to verify that it showed what you thought it should.

So if I may guess, what I think you meant to say was, "there's no way you'd be able to convince yourself that the schematic was correct." Is that right? I can believe that you are right, but it would be helpful to understand why. Is it because the schematic would be huge? Or because the logic would be incomprehensible (even if correct) because it was synthesized automatically? Or all of the above? Or something else?

-- Russ