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???
11/13/06 08:22
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#127860 - And times change
Responding to: ???'s previous message
Richard Erlacher said:

Keep in mind that senior engineers went to school before there was 'C' and before there was VHISIC and VHDL. They were working with DTL and RTL if not relays.


So does that mean that young whizz-kid engineers have to stick to the same archaic design methods just to respect the elderly?

Richard Erlacher said:

I once lived on "evaluation boards" which I could string together in order to build large and complex functional systems in order to prove concepts, and, afterward, tear them down and put them back on the shelf and use them again later. Todays eval boards are like 10 pounds of sh*t in a 5-pound bag, with the "features" always in the way.


Nobody is stopping you form building your own small PCB with just the PLD, regulator and oscillator on it.

Richard Erlacher said:

If it weren't for the short market life of current-generation programmable logic, I'd just build my own boards.


Yeah sure. Just because there are new PLD generations, doen't mean that the 'old' ones become obsolete. We still do some proof of concept on Cyclone I&II boards while the product might use a StratixII or in some time StratixIII. Another project we did the ramp-up on an existing VirtexII board and the moved to a Spartan3. Thats the nice thing about FPGAs, a previous project might serve as a start for a new one.

Richard Erlacher said:

The way this thread started, the O/P was asking about how to get started. Well, I've always believed that a board with just the minimal amount of hardware would suit best.


Sure, because implementing something like a VGA pattern generator is so complicated and only to be attempted by people that have their Ph.D. for at least ten years.
What would Russ want with just some switches and LED's? after some time one can be fed up of all the knight rider blink patterns and might try something new.

Richard Erlacher said:

Guys who haven't been doing programmable logic have been drawing schematics with discrete (MSI/SSI) logic and MCU's. For them to abandon what they've been doing and start over, cold, in an unfamiliar HDL is too much "future shock" for them, IMHO, so that's why I've promoted sticking with schematic entry.


And thats bollocks! Now it's new, time to learn, better let them start with the way how it's done, rather than seducing them to the dark side where they have a difficulty to escape from.

Good for you that you have to use schematics, the perfect way of designing since the dawn of time, but don't enforce that on someone new, who still has the chance to do it right, and pray that he has never to endure the same customers as you do.

Somebody who knows discrete circuit design (your MCU projects with the occasional 74 pepper) and then give them a FPGA again with a schematic tool, perfect recipe for disaster.

Richard Erlacher said:

It will get him familiarized with simulation, testbenches, and prepare him for the somewhat more murky world of FPGA application.


if you've never understood how to design for FPGAs, ofcourse their world is murky.

Richard Erlacher said:

There are reasons why I think it appropriate in this context, and there are reasons why I use 'em as much as I do in my work. It's because the meet my needs and satisfy my clients' needs.


You say, because you have no choice, and thats an entirely different thing. Why enavngelize something that is plain wrong on everybody else? If Russ wan't to use schematics, fine, his choice, but i say he'll find himself in a dead end.

Cheers, Roger



List of 81 messages in thread
TopicAuthorDate
Getting Started With FPGAs            01/01/70 00:00      
   A Book            01/01/70 00:00      
   Proceed with caution!            01/01/70 00:00      
   This is quite a nice deveolpment board            01/01/70 00:00      
   I like this board            01/01/70 00:00      
      I\'ve got one of these and can\'t recommend it            01/01/70 00:00      
         What are you talking about            01/01/70 00:00      
            Let me explain ...            01/01/70 00:00      
   generaly speaking            01/01/70 00:00      
      Damn, Jez, you need a spell-checker!            01/01/70 00:00      
         HDL-based design needs TEST BENCHES            01/01/70 00:00      
            I use 'em all the time, but ...            01/01/70 00:00      
               If your design is so simple            01/01/70 00:00      
                  What\'s important is the entry effort            01/01/70 00:00      
                     I dunno where you get these ideas from Richard            01/01/70 00:00      
                        Can you say ModelSim?            01/01/70 00:00      
                     Wrong            01/01/70 00:00      
                        Well, the schematic needs a little work            01/01/70 00:00      
                           more work?            01/01/70 00:00      
                              a few points ...            01/01/70 00:00      
                           ...            01/01/70 00:00      
                     HDL vs Schematics, take 1E6            01/01/70 00:00      
                        Thta may be great comfort to you ...            01/01/70 00:00      
                           Schematics? You're kidding!            01/01/70 00:00      
                              No, nor is my customer.            01/01/70 00:00      
                              both are a 'representation of Boole'            01/01/70 00:00      
                                 Yep, you're right...            01/01/70 00:00      
                                    To Clarify            01/01/70 00:00      
                                       schematic as equivalence check            01/01/70 00:00      
                                          Manual verification impossible because ...            01/01/70 00:00      
                                             schematic verification            01/01/70 00:00      
                                       Some more clarification            01/01/70 00:00      
                                          hanging problem            01/01/70 00:00      
                                             so will your post be            01/01/70 00:00      
                                    it's not fear of the unknown, but fear of its cost            01/01/70 00:00      
                           Static Timing Analysis and those "young engineers"            01/01/70 00:00      
                              It's a sign of the times, I suppose            01/01/70 00:00      
                                 And times change            01/01/70 00:00      
                                 senior?            01/01/70 00:00      
                                    That's because you've been avoiding the subject            01/01/70 00:00      
            I agree entirely. test benches are a pain but            01/01/70 00:00      
   Update from the OP            01/01/70 00:00      
      It's true ... we see things differently            01/01/70 00:00      
      the first buuk for any such venture            01/01/70 00:00      
      FPGA boards and that Cypress book            01/01/70 00:00      
         This may answer your question(s)            01/01/70 00:00      
   some of the references in the fpga faq            01/01/70 00:00      
      Good attitude            01/01/70 00:00      
   Also remeber to look at webistes like www.xilinx.c            01/01/70 00:00      
   My recommendation and opinions            01/01/70 00:00      
      I would stay away from Virtex-II            01/01/70 00:00      
         If you're going to fiddle with the 805x core ...            01/01/70 00:00      
            Something about life-cycles            01/01/70 00:00      
               No doubt about it.            01/01/70 00:00      
                  useful work            01/01/70 00:00      
                     Well, I beg to differ.            01/01/70 00:00      
                        salient point            01/01/70 00:00      
                           There's an area where that's not necessarily true            01/01/70 00:00      
                           FPGA Editor            01/01/70 00:00      
            Not necessarily            01/01/70 00:00      
               It's still too costly            01/01/70 00:00      
   Thanks to all            01/01/70 00:00      
   Update #2 from the OP            01/01/70 00:00      
   A testbench is...            01/01/70 00:00      
      I C            01/01/70 00:00      
         test bench            01/01/70 00:00      
            Makes sense            01/01/70 00:00      
   Yeah but...            01/01/70 00:00      
   Tristate buffer with propagation delays            01/01/70 00:00      
   Schematics vs. HDL            01/01/70 00:00      
      In a nutshell            01/01/70 00:00      
         it\'s been a while            01/01/70 00:00      
      Yes, but ... and there's always a but ...            01/01/70 00:00      
   Yep you can its called gate level design            01/01/70 00:00      
   Its really nothing to do with showing off            01/01/70 00:00      
      did you paraphrase this?            01/01/70 00:00      
      Jez, It\'s not \"sea of gates\" design, you know ...            01/01/70 00:00      
         Richards, it is there philosophy            01/01/70 00:00      
         Viewlogic            01/01/70 00:00      
   it is true            01/01/70 00:00      
   Here you go Richard graphical design exploration            01/01/70 00:00      

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