I've had considerable exposure to HDL's. Probably over a longer period than you, which is what makes me cautious about recommending 'em to my clients. I have several 3rd-party tools at my disposal, but can't recommend 'em to my clients because of their cost. The vendor-supplied tools, from Xilinx, Altera, Actel, and Lattice, are a disappointment. They're useable but a disappointment nonetheless.

However, recent experience, where we've hired VHDL "experts" to aid in reviews, they've never agreed on what a given VHDL design was written to do. My complaint, all along, has been that the schematic package, with which one can prepare an easily reviewable set of specifications, has, in the XILINX case, proven in recent releases, to be a piece of rubbish. The sad thing is, in earlier releases, that was not the case. It wasn't perfect, and one had to close the file and then reopen it, quite routinely, to make the errors go away.


They used Quine-McLuskey, which was the established and popular algorithm of the time. Later versions used another algorithm, one that I've never looked at but which apparently worked better.I never even once had to " break out the K-maps and do it" myself. K-maps are fine for, say, up to four variables, but after that they're so confusing they're no help. When I had equations in a dozen variables, I didn't like trying things I knew wouldn't work.


Perhaps you can explain what, exactly, made that version, for its time, so "limited." The Cypress CPLD's were the biggest available and allowed numerous important things unattainable with FPGA's at the time, such as deterministic timing and pre-design pin locking. I can remember one XILINX-based board, back in '90,that had 11 FPGA's on it, yet required nearly a dozen wires per FPGA (and they didn't have that many pins, back then) to compensate for timing changes due to routing. XILINX didn't even have VHDL yet ... Altera had AHDL, and Cypress had WARP. Everything serious was done with schematics back then ...



You keep accusing me of denegrating the language, and, HDL's in general. That's not the case. I'm just not happy with the vendor-provided tools.

That's no reflection on the languages.

It simply means that, because K-12 institutions aren't teaching proper organization skills, reflected in writing proper HDL and/or drawing proper schematics, and colleges shouldn't really have to do that, people graduate from college with engineering degrees without even the first notion of how to read, much less create, a proper schematic. This same weakness is reflected in their composition of written work, and their 'C' and C++ programming, as well as their creation of HDL work.

Further, they graduate with the very erroneous belief that having that sheepskin makes them an "expert" on something, though, in many cases, they've not even learned the most basic thing, namely how to learn. Not only are they really bad engineers, but they'll never improve, because they don't know how, nor do they understand that they must.

RE